feat(qc_iu): Add Xqccmi custom compressed instruction lookup table extension by ayosher · Pull Request #1802 · riscv/riscv-unified-db

ayosher · 2026-04-23T13:59:23Z

Introduces the Xqccmi extension for the qc_iu configuration. Xqccmi improves code density by replacing frequently-used 32-bit (and wider) instructions with a single 16-bit lookup instruction, qc.cm.ilut, that fetches and executes the original instruction from a table in memory.

The table (Instruction Lookup Table, ILUT) is an array of entries in memory whose base address is configured by a new CSR, qc.itba. A linker or post-processing tool populates the table with the most-used instruction encodings and replaces each occurrence in the code stream with a 16-bit qc.cm.ilut instruction carrying an 11-bit index (0..2047) into the table. The net effect is that a 32-bit or wider instruction is replaced by a 16-bit one wherever it appears, reducing code size.

Each table entry can hold one or two packed instructions:

A 32-bit entry holds one 32-bit instruction, or two 16-bit instructions
A 64-bit entry (double entry) holds combinations up to 64 bits total, including 48-bit Xqci instructions. The number of leading 64-bit entries is configured by a second new CSR, qc.itdec.

When a table entry contains two instructions and the second instruction causes an exception or double trap, bit 0 of mepc (or mnepc) is set to

This allows software to identify which instruction within the entry was the source of the fault, enabling precise exception handling and software emulation of absent instructions.

qc.cm.ilut uses the same encoding as c.fld and is therefore mutually exclusive with the Zcd extension.

Key changes:

Added extension definition: spec/custom/isa/qc_iu/ext/Xqccmi.yaml
Added instruction: spec/custom/isa/qc_iu/inst/Xqccmi/qc.cm.ilut.yaml
Added CSR qc.itba (0x800): spec/custom/isa/qc_iu/csr/Xqccmi/qc.itba.yaml
Added CSR qc.itdec (0x801): spec/custom/isa/qc_iu/csr/Xqccmi/qc.itdec.yaml
Updated cfgs/qc_iu.yaml to include Xqccmi v0.1.0

…tension Introduces the Xqccmi extension for the qc_iu configuration. Xqccmi improves code density by replacing frequently-used 32-bit (and wider) instructions with a single 16-bit lookup instruction, qc.cm.ilut, that fetches and executes the original instruction from a table in memory. The table (Instruction Lookup Table, ILUT) is an array of entries in memory whose base address is configured by a new CSR, qc.itba. A linker or post-processing tool populates the table with the most-used instruction encodings and replaces each occurrence in the code stream with a 16-bit qc.cm.ilut instruction carrying an 11-bit index (0..2047) into the table. The net effect is that a 32-bit or wider instruction is replaced by a 16-bit one wherever it appears, reducing code size. Each table entry can hold one or two packed instructions: - A 32-bit entry holds one 32-bit instruction, or two 16-bit instructions - A 64-bit entry (double entry) holds combinations up to 64 bits total, including 48-bit Xqci instructions. The number of leading 64-bit entries is configured by a second new CSR, qc.itdec. When a table entry contains two instructions and the second instruction causes an exception or double trap, bit 0 of mepc (or mnepc) is set to 1. This allows software to identify which instruction within the entry was the source of the fault, enabling precise exception handling and software emulation of absent instructions. qc.cm.ilut uses the same encoding as c.fld and is therefore mutually exclusive with the Zcd extension. Key changes: - Added extension definition: spec/custom/isa/qc_iu/ext/Xqccmi.yaml - Added instruction: spec/custom/isa/qc_iu/inst/Xqccmi/qc.cm.ilut.yaml - Added CSR qc.itba (0x800): spec/custom/isa/qc_iu/csr/Xqccmi/qc.itba.yaml - Added CSR qc.itdec (0x801): spec/custom/isa/qc_iu/csr/Xqccmi/qc.itdec.yaml - Updated cfgs/qc_iu.yaml to include Xqccmi v0.1.0 Signed-off-by: Albert Yosher <181945086+ayosher@users.noreply.github.com>

codecov · 2026-04-23T14:00:58Z

Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 72.21%. Comparing base (287f86c) to head (3252d57).
⚠️ Report is 2 commits behind head on main.

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ayosher · 2026-04-29T18:27:49Z

Hi, I know, and I did for some bitfields. In the specific case, I want to declare these bits as "mode" to be forward compatible and visible in the generated PDF doc. Is this an issue? Albert

________________________________ From: Paul Clarke ***@***.***> Sent: Wednesday, April 29, 2026 9:24 PM To: riscv/riscv-unified-db ***@***.***> Cc: Albert Yosher (QUIC) ***@***.***>; Author ***@***.***> Subject: Re: [riscv/riscv-unified-db] feat(qc_iu): Add Xqccmi custom compressed instruction lookup table extension (PR #1802) WARNING: This email originated from outside of Qualcomm. Please be wary of any links or attachments, and do not enable macros. @ThinkOpenly commented on this pull request.

________________________________ In spec/custom/isa/qc_iu/csr/Xqccmi/qc.itba.yaml<#1802 (comment)>:

+ mode:

+ location: 5-0 + type: RO + reset_value: 0 + description: | + Reserved for future use. Always reads as zero. Writes are ignored. You probably don't need to specify this. Undefined bits default to reserved, read-only. — Reply to this email directly, view it on GitHub<#1802 (review)>, or unsubscribe<https://github.com/notifications/unsubscribe-auth/BLMEF7WF43BL64XEPAQOSCT4YJCGZAVCNFSM6AAAAACYD4U7SSVHI2DSMVQWIX3LMV43YUDVNRWFEZLROVSXG5CSMV3GSZLXHM2DCOJZGY2DKOBQG4>. Triage notifications on the go with GitHub Mobile for iOS<https://apps.apple.com/app/apple-store/id1477376905?ct=notification-email&mt=8&pt=524675> or Android<https://play.google.com/store/apps/details?id=com.github.android&referrer=utm_campaign%3Dnotification-email%26utm_medium%3Demail%26utm_source%3Dgithub>. You are receiving this because you authored the thread.Message ID: ***@***.***>

Custom extensions in development state are never formally ratified; the `ratification_date` field is not applicable. Remove it per review feedback. Signed-off-by: Albert Yosher <ayosher@qti.qualcomm.com>

qc.itba: use location_rv32/location_rv64 instead of a single location field for the BASE field, matching the description text "bits[XLEN-1:6]" and the pattern used in the standard jvt.yaml. qc.itdec: replace variable name N with DEC throughout the description text to avoid using two names for the same field. qc.cm.ilut: add PC-relative instruction detection and proper mepc/mnepc bit 0 encoding for exception slot attribution: - Add is_pc_relative_inst?() to qc_iu globals.isa: detects forbidden PC-relative instructions in ILUT entries across all encoding widths: 16-bit compressed (c.j, c.jal, c.jr, c.jalr, c.beqz, c.bnez), 32-bit (auipc, jal, jalr, branches), and 48-bit Xqci (qc.e.j, qc.e.jal, qc.e.beqi/bnei/blti/bgei/ bltui/bgeui). Implemented as a named reusable function rather than inline opcode checks, so future instructions are handled by updating one place. - Add ilut_second_inst global boolean and raise_ilut() function to qc_iu globals.isa. raise_ilut() is a simplified M-mode-only variant of raise_precise() that sets mepc.PC (or mnepc.PC for a double-trap) to $pc | (ilut_second_inst ? 1 : 0), encoding which packed instruction slot caused the exception in bit 0. - Replace all raise() calls in qc.cm.ilut operation() with raise_ilut(), setting ilut_second_inst appropriately before each call: false for the first instruction slot (48-bit doesn't fit, first PC-relative check, first instruction execution), true for the second instruction slot (second PC-relative check, second instruction execution). - Add mepc.yaml and Smrnmi/mnepc.yaml overlays for qc_iu to remove the standard bit-0 mask on sw_write and sw_read, allowing raise_ilut() to preserve bit 0 of mepc/mnepc. All changes validated: test:schema, test:inst_encodings, test:idl CFG=qc_iu, and bin/regress --tag smoke (11/11) pass. Signed-off-by: Albert Yosher <181945086+ayosher@users.noreply.github.com>

- Xqccmi.yaml: add top-level requirements to express mutual exclusivity with Zcd extension - qc.cm.ilut.yaml: initialize entry_hi = 32'b0 (remove else branch); rename has_second -> has_second_inst with inline comment; rename ilut_second_inst -> executing_second_inst throughout; clean up duplicate/stale comments in execution blocks; clarify that IDL cannot express dynamic instruction dispatch - globals.isa: rename ilut_second_inst -> executing_second_inst; update declaration comment to reflect new name and purpose Files modified: - spec/custom/isa/qc_iu/ext/Xqccmi.yaml - spec/custom/isa/qc_iu/inst/Xqccmi/qc.cm.ilut.yaml - spec/custom/isa/qc_iu/isa/globals.isa

Signing off review comment requested change Co-authored-by: Paul Clarke <ThinkOpenly@gmail.com> Signed-off-by: ayosher <181945086+ayosher@users.noreply.github.com>

- qc.cm.ilut.yaml: mark unpredictable() calls as TO-DO to make clear they are placeholders pending a real execute_instruction() builtin - globals.isa: fix bug in is_pc_relative_inst?() — c.jr, c.jalr, and 32-bit jalr are register-indirect jumps, not PC-relative; remove them from the forbidden instruction list and update the description Signed-off-by: Albert Yosher <181945086+ayosher@users.noreply.github.com>

ayosher requested review from ThinkOpenly and dhower-qc as code owners April 23, 2026 13:59

ayosher added 2 commits April 28, 2026 09:25

Merge branch 'main' into ayosher_xqccmi_0_1_0

719dec8

Merge branch 'main' into ayosher_xqccmi_0_1_0

357151b

dhower-qc approved these changes Apr 29, 2026

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dhower-qc enabled auto-merge April 29, 2026 18:20

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Comment thread spec/custom/isa/qc_iu/csr/Xqccmi/qc.itba.yaml

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Comment thread spec/custom/isa/qc_iu/ext/Xqccmi.yaml Outdated

fix(Xqccmi): remove ratification_date from development extension

55bc7bb

Custom extensions in development state are never formally ratified; the `ratification_date` field is not applicable. Remove it per review feedback. Signed-off-by: Albert Yosher <ayosher@qti.qualcomm.com>

auto-merge was automatically disabled April 29, 2026 18:55
Head branch was pushed to by a user without write access

Merge branch 'main' into ayosher_xqccmi_0_1_0

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Comment thread spec/custom/isa/qc_iu/csr/Xqccmi/qc.itba.yaml Outdated

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Comment thread spec/custom/isa/qc_iu/csr/Xqccmi/qc.itdec.yaml Outdated

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Comment thread spec/custom/isa/qc_iu/inst/Xqccmi/qc.cm.ilut.yaml

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