Use regfile YAMLs for F, V; enhance trusim to understand by dhower-qc · Pull Request #1813 · riscv/riscv-unified-db

dhower-qc · 2026-04-29T17:57:23Z

No description provided.

codecov · 2026-04-29T17:59:47Z

Codecov Report

❌ Patch coverage is 65.95745% with 16 lines in your changes missing coverage. Please review.
✅ Project coverage is 72.23%. Comparing base (7d85d71) to head (8342107).

Files with missing lines	Patch %	Lines
tools/ruby-gems/udb/lib/udb/obj/register_file.rb	48.27%	15 Missing ⚠️
tools/ruby-gems/udb/lib/udb/cfg_arch.rb	94.44%	1 Missing ⚠️

Additional details and impacted files

@@            Coverage Diff             @@
##             main    #1813      +/-   ##
==========================================
+ Coverage   72.18%   72.23%   +0.04%     
==========================================
  Files          52       52              
  Lines       27744    27770      +26     
  Branches     6002     5999       -3     
==========================================
+ Hits        20028    20059      +31     
+ Misses       7716     7711       -5

Flag	Coverage Δ
udb	`66.37% <65.95%> (+0.12%)`	⬆️

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Pull request overview

This PR migrates register-file modeling to be driven by register_file YAMLs (not hardcoded IDL globals), generalizes IDLC’s type/symbol system to support multiple register files (X/F/V), and updates the C++ ISS/hart generator pipeline accordingly.

Changes:

Replace register-file width metadata with a register_length() IDL-function-body field and introduce per-register reset_value.
Generalize IDLC symbol table/types and register-access analysis to handle arbitrary register files (not just X).
Update ISA specs and C++ generator/ISS integration to use YAML-defined F/V/X register files; add targeted Ruby/C++ tests.

Reviewed changes

Copilot reviewed 80 out of 80 changed files in this pull request and generated 5 comments.

Show a summary per file

File	Description
tools/ruby-gems/udb/test/test_register_file_obj.rb	Adds unit tests for new RegisterFile/RegisterEntry behaviors (register_length(), reset_value, backrefs, width eval).
tools/ruby-gems/udb/test/run.rb	Includes the new RegisterFile object-model tests in the udb test runner.
tools/ruby-gems/udb/lib/udb/obj/register_file.rb	Implements `register_length()` parsing/eval, `max_register_length`, `reset_value`, and entry back-reference.
tools/ruby-gems/udb/lib/udb/cfg_arch.rb	Adds symtab-construction reentrancy guards and precomputes register-file max widths for the IDL symtab.
tools/ruby-gems/udb/lib/udb/architecture.rb	Updates register-file loader directory from `register` to `register_file`.
tools/ruby-gems/idlc/test/test_values.rb	Adds tests for ternary `max_value`/`min_value` used by register-width max derivation.
tools/ruby-gems/idlc/test/test_register_files.rb	Adds IDLC tests for generalized register-file globals/types and src/dst register discovery.
tools/ruby-gems/idlc/test/run.rb	Includes the new IDLC register-file tests in the idlc test runner.
tools/ruby-gems/idlc/test/helpers.rb	Introduces a minimal X register-file test double and wires it into the shared test symtab setup.
tools/ruby-gems/idlc/lib/idlc/type.rb	Introduces `RegFileElementType` and keeps `XregType` as a backwards-compatible alias.
tools/ruby-gems/idlc/lib/idlc/symbol_table.rb	Adds `register_files:` + `register_file_max_widths:` to define global arrays/types for RFs (X/F/V/etc.).
tools/ruby-gems/idlc/lib/idlc/passes/find_src_registers.rb	Generalizes register read/write discovery to return `[rf_name, index]` pairs for any RF global.
tools/ruby-gems/idlc/lib/idlc/cli.rb	Ensures CLI symtab always has a default X register file.
tools/ruby-gems/idlc/lib/idlc/ast.rb	Adjusts global symbol registration order and generalizes const-eval checks and ternary min/max evaluation.
spec/std/isa/register_file/X.yaml	Converts to `register_length()` and adds `reset_value` for x0.
spec/std/isa/register_file/V.yaml	Converts to `register_length()` form for VLEN-based width.
spec/std/isa/register_file/F.yaml	Converts to `register_length()` with an implemented?(D) ternary width.
spec/std/isa/param/VLEN.yaml	Adds explicit min/max bounds for VLEN.
spec/std/isa/isa/vec.idl	Removes hardcoded `v[32]` and notes symtab/YAML population.
spec/std/isa/isa/fp.idl	Removes hardcoded FP regfile init and keeps FLEN derived from implemented?(D).
spec/std/isa/inst/Zfh/fsh.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/Zfh/fmv.x.h.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/Zfh/fmv.h.x.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/Zfh/flh.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/Zfh/fcvt.s.h.yaml	Updates FP regfile access from `f[...]` to `F[...]` (including comments).
spec/std/isa/inst/Zfh/fcvt.h.s.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/Zfa/fround.s.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/Zcf/c.fswsp.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/Zcf/c.flwsp.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/Zcd/c.fsdsp.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/Zcd/c.fldsp.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/Zcd/c.fld.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/V/vse8.v.yaml	Updates vector regfile access from `v[...]` to `V[...]`.
spec/std/isa/inst/V/vmv.x.s.yaml	Updates vector regfile access from `v[...]` to `V[...]`.
spec/std/isa/inst/V/vmv.v.i.yaml	Updates vector regfile access from `v[...]` to `V[...]` (including comments).
spec/std/isa/inst/V/vle8.v.yaml	Updates vector regfile access from `v[...]` to `V[...]`.
spec/std/isa/inst/V/vadd.vv.yaml	Updates vector regfile access from `v[...]` to `V[...]`.
spec/std/isa/inst/F/fsw.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/fsub.s.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/fsqrt.s.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/fsgnjx.s.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/fsgnjn.s.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/fsgnj.s.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/fnmsub.s.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/fnmadd.s.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/fmv.x.w.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/fmv.w.x.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/fmul.s.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/fmsub.s.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/fmin.s.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/fmax.s.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/fmadd.s.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/flw.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/fltq.s.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/flt.s.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/fleq.s.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/fle.s.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/feq.s.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/fdiv.s.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/fcvt.wu.s.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/fcvt.w.s.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/fcvt.s.wu.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/fcvt.s.w.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/fcvt.s.lu.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/fcvt.s.l.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/fcvt.lu.s.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/fcvt.l.s.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/fclass.s.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/std/isa/inst/F/fadd.s.yaml	Updates FP regfile access from `f[...]` to `F[...]`.
spec/schemas/register_file_schema.json	Updates schema for `register_length()` and adds `reset_value` support.
backends/cpp_hart_gen/templates/inst.hxx.erb	Updates src/dst register enumeration to use rf-aware pairs.
backends/cpp_hart_gen/templates/hart_impl.hxx.erb	Adjusts global instantiation and printState to iterate over register files.
backends/cpp_hart_gen/templates/hart.hxx.erb	Generates storage/accessors for all register files and applies reset_value initialization.
backends/cpp_hart_gen/tasks.rake	Adds `test_regfile` to the backend test task.
backends/cpp_hart_gen/lib/template_helpers.rb	Adds helpers for RF width/type compilation and arch read/write/reset generation.
backends/cpp_hart_gen/lib/gen_cpp.rb	Generalizes array-element C++ generation for any RF global array.
backends/cpp_hart_gen/cpp/test/test_regfile.cpp	Adds Catch2 tests verifying X/F regfile storage/accessors via HartFactory.
backends/cpp_hart_gen/cpp/src/iss.cpp	Implements FPR read/write through the hart (instead of returning -1).
backends/cpp_hart_gen/cpp/include/udb/hart.hpp	Adds virtual `freg/set_freg` and `vreg/set_vreg` hooks to HartBase with default throws.
backends/cpp_hart_gen/CMakeLists.txt	Adds `test_regfile` target and registers it with CTest/Catch discovery.

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ThinkOpenly · 2026-04-29T23:57:54Z

 register_class: floating_point
-register_length: FLEN
+register_length(): |
+  return implemented?(ExtensionName::D) ? 64 : 32;


Do we need to accommodate "Q" here (FLEN=128)?

good point, yes we do

ThinkOpenly · 2026-04-30T00:00:34Z

-                    0, 0, 0, 0, 0, 0, 0, 0,
-                    0, 0, 0, 0, 0, 0, 0, 0,
-                    0, 0, 0, 0, 0, 0, 0, 0];
+U32 FLEN = implemented?(ExtensionName::D) ? 7'd64 : 7'd32;


Do we need to accommodate "Q" here?

henrikg-qc

Can you add vector regs to the GDB XML registers

Not a must as I can do it later but if the ISS now support vector it would be complete

Use regfile YAMLs for F, V; enhance trusim to understand

b0ae511

Copilot AI review requested due to automatic review settings April 29, 2026 17:57

dhower-qc requested a review from ThinkOpenly as a code owner April 29, 2026 17:57

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dhower-qc added 2 commits April 29, 2026 12:55

Merge remote-tracking branch 'origin/main' into regfile

e6551f6

fix ci errors

f6da17b

ThinkOpenly reviewed Apr 29, 2026

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ThinkOpenly reviewed Apr 30, 2026

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address review comments

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dhower-qc requested review from Copilot and henrikg-qc May 6, 2026 16:48

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dhower-qc and others added 5 commits May 6, 2026 10:00

Merge remote-tracking branch 'origin/main' into regfile

5548c71

[autofix.ci] apply automated fixes

83c3688

add missing _value

aa14319

Merge remote-tracking branch 'dhower-qc/regfile' into regfile

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[autofix.ci] apply automated fixes

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Use regfile YAMLs for F, V; enhance trusim to understand#1813

Use regfile YAMLs for F, V; enhance trusim to understand#1813
dhower-qc wants to merge 9 commits intoriscv:mainfrom
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