Add support for the Zvksed extension #245
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…iscv#191) * V extension general framework and configuration setting instructions * Update model/riscv_insts_vext_utils.sail fix a typo Co-authored-by: Nicolas Brunie <[email protected]> Signed-off-by: BrighterW <[email protected]> * Update model/riscv_insts_vext_vset.sail * Revisions after Nov 22 meeting * Update effect matching for functions in riscv_vlen.sail * Fix code formatting issues * Update model/riscv_insts_vext_utils.sail Co-authored-by: Jessica Clarke <[email protected]> Signed-off-by: Xinlai Wan <[email protected]> * Fix coding style issues * Update vset instructions Signed-off-by: BrighterW <[email protected]> Signed-off-by: Xinlai Wan <[email protected]> Co-authored-by: Nicolas Brunie <[email protected]> Co-authored-by: Jessica Clarke <[email protected]>
* Add vector load / store instructions * Modify the implementation of SEW, LMUL, VLEN and avoid real numbers in the code * Update vstart setting in vector load / store instructions * Remove unnecessary assert statements in vector instructions * Fix bugs in vleff instructions and revise coding styles * Add guards for vector encdec clauses, Avoid redundant memory access after vector load/store failure
* Add vector arithmetic & mask instructions * Update vector EEW and EMUL checking function * Add vector instruction illegal check functions * Adjust code formatting for vector instruction illegal check functions Merge approved by team at tech-golden-model meeting on 2023-03-14.
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Updated the PR:
This update is adjusting the implementation to match the Spike implenentation and as a follow-up, ACT Signatures matching. |
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* Add vector floating-point instructions * Update vector floating-point conversion instructions * Update copyright headers for vector extension code --------- Co-authored-by: xwan <[email protected]>
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* Add vector mask and reduction instructions * Fix register overlap check in vector mask instructions --------- Co-authored-by: xwan <[email protected]>
To support the implementation of the Zvksed extension in SAIL, this creates the necessary infrastructure (i.e., a file to hold it, and the existence macro), preparing the tree for the Zvksed implementation. Signed-off-by: Charalampos Mitrodimas <[email protected]>
Vector SM4 KeyExpansion, four rounds of the SM4 Key expansion are performed. Note: zvksed_box_lookup & zvksed_sm4_sbox are created to work with 32bit values since sbox_lookup & sm4_sbox are used for 8bit values. The bits in uimm[4..3] are ignored. Round group numbers range from 0 to 7 and indicate which group of four round keys are being generated. Signed-off-by: Charalampos Mitrodimas <[email protected]>
Vector SM4 Rounds, four rounds of SM4 Encryption/Decryption are performed. The four words of current state are read in as a 4-element group from 'vd' and the round keys are read in from the corresponding 4-element group in vs2 (vector-vector form) or the scalar element group in vs2 (vector-scalar form). The next four words of state are generated by iteratively XORing the last three words of the state with the corresponding round key, performing a byte-wise substitution, and then performing XORs between rotated versions of this value and the corresponding current state. Signed-off-by: Charalampos Mitrodimas <[email protected]>
Signed-off-by: Charalampos Mitrodimas <[email protected]>
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Implements the Zvksed (ShangMi Suite: SM4 Block Cipher) extension, as of version Draft: 20230303
The following instructions are included:
All instructions were tested with VLEN & ELEN being manually adjusted; results were compared with QEMU results of each instruction.
Current revision is rebased with the latest changes of
vector-devbranch.