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RISCV: Add vector psabi checking. #376

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72 changes: 72 additions & 0 deletions gcc/config/riscv/riscv.cc
Original file line number Diff line number Diff line change
Expand Up @@ -3728,6 +3728,75 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1,
GEN_INT (offset2))));
}

/* Use the TYPE_SIZE to distinguish the type with vector_size attribute and
intrinsic vector type. Because we can't get the decl for the params. */

static bool
riscv_arg_has_vector_size_attribute (const_tree type)
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riscv_scalable_vector_type_p

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Done.

{
tree size = TYPE_SIZE (type);
if (size && TREE_CODE (size) == INTEGER_CST)
return true;

/* For the data type like vint32m1_t, the size code is POLY_INT_CST. */
return false;
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The return value should be inverted after function rename :)

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Oh understand. Could I know why the intrinsic vector type is named as scalable vector ?

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that's the term defined in AArch64 SVE actually, and we follow to use that term in our backend too , e.g. riscv.cc:riscv_v_adjust_scalable_frame

}

static bool
riscv_arg_has_vector (const_tree type)
{
bool is_vector = false;

switch (TREE_CODE (type))
{
case RECORD_TYPE:
if (!COMPLETE_TYPE_P (type))
break;

for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
if (TREE_CODE (f) == FIELD_DECL)
{
if (!TYPE_P (TREE_TYPE (f)))
break;

/* If there's vector_size attribute, ignore it. */
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Ignore it if it's fixed length vector.

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Done.

if (VECTOR_TYPE_P (TREE_TYPE (f)))
is_vector = !riscv_arg_has_vector_size_attribute (type);
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riscv_arg_has_vector_size_attribute (TREE_TYPE (f))?

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Thanks, you're right. It should be the field type.

else
is_vector = riscv_arg_has_vector (TREE_TYPE (f));
}

break;

case VECTOR_TYPE:
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is_vector = !riscv_arg_has_vector_size_attribute (type);
break;

default:
is_vector = false;
break;
}

return is_vector;
}

/* Pass the type to check whether it's a vector type or contains vector type.
Only check the value type and no checking for vector pointer type. */

static void
riscv_pass_in_vector_p (const_tree type)
{
static int warned = 0;
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if (type && riscv_arg_has_vector (type) && !warned)
{
warning (OPT_Wpsabi, "ABI for the vector type is currently in "
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vector -> scalable vector, that should more clear that it's exclude fixed length vector.

"experimental stage and may changes in the upcoming version of "
"GCC.");
warned = 1;
}
}

/* Fill INFO with information about a single argument, and return an
RTL pattern to pass or return the argument. CUM is the cumulative
state for earlier arguments. MODE is the mode of this argument and
Expand Down Expand Up @@ -3812,6 +3881,9 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,
}
}

/* Only check existing of vector type. */
riscv_pass_in_vector_p (type);

/* Work out the size of the argument. */
num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode).to_constant ();
num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
Expand Down
14 changes: 14 additions & 0 deletions gcc/testsuite/gcc.target/riscv/vector-abi-1.c
Original file line number Diff line number Diff line change
@@ -0,0 +1,14 @@
/* { dg-do compile } */
/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */

#include "riscv_vector.h"

void
fun (vint32m1_t a) { } /* { dg-warning "the vector type" } */

void
bar ()
{
vint32m1_t a;
fun (a);
}
14 changes: 14 additions & 0 deletions gcc/testsuite/gcc.target/riscv/vector-abi-2.c
Original file line number Diff line number Diff line change
@@ -0,0 +1,14 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d" } */

#include "riscv_vector.h"

vint32m1_t
fun (vint32m1_t* a) { return *a; } /* { dg-warning "the vector type" } */
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void
bar ()
{
vint32m1_t a;
fun (&a);
}
14 changes: 14 additions & 0 deletions gcc/testsuite/gcc.target/riscv/vector-abi-3.c
Original file line number Diff line number Diff line change
@@ -0,0 +1,14 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d" } */

#include "riscv_vector.h"

vint32m1_t*
fun (vint32m1_t* a) { return a; } /* { dg-bogus "the vector type" } */

void
bar ()
{
vint32m1_t a;
fun (&a);
}
16 changes: 16 additions & 0 deletions gcc/testsuite/gcc.target/riscv/vector-abi-4.c
Original file line number Diff line number Diff line change
@@ -0,0 +1,16 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d" } */

#include "riscv_vector.h"

typedef int v4si __attribute__ ((vector_size (16)));

v4si
fun (v4si a) { return a; } /* { dg-bogus "the vector type" } */

void
bar ()
{
v4si a;
fun (a);
}
15 changes: 15 additions & 0 deletions gcc/testsuite/gcc.target/riscv/vector-abi-5.c
Original file line number Diff line number Diff line change
@@ -0,0 +1,15 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d" } */

typedef int v4si __attribute__ ((vector_size (16)));
struct A { int a; v4si b; };

void
fun (struct A a) {} /* { dg-bogus "the vector type" } */

void
bar ()
{
struct A a;
fun (a);
}