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@rits-drsl

rits-drsl

Dynamic Reconfigurable System Lab., Ritsumeikan Univ.

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  1. ZybotR2-96-fpt19 ZybotR2-96-fpt19 Public

    An UGV-system using SoC-FPGA developed for FPGA design competition held on ICFPT2019

    C++ 17 2

  2. ZybotR2-96-fpt19-bsp ZybotR2-96-fpt19-bsp Public

    Board Support Packages for rits-drsl/ZybotR2-96-fpt19

    C

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  • ZybotR2-96-fpt19 Public

    An UGV-system using SoC-FPGA developed for FPGA design competition held on ICFPT2019

    rits-drsl/ZybotR2-96-fpt19’s past year of commit activity
    C++ 17 MIT 2 0 0 Updated Jun 15, 2020
  • ZybotR2-96-fpt19-bsp Public

    Board Support Packages for rits-drsl/ZybotR2-96-fpt19

    rits-drsl/ZybotR2-96-fpt19-bsp’s past year of commit activity
    C 0 MIT 0 0 0 Updated Dec 12, 2019

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