Skip to content
View rockymoo's full-sized avatar

Block or report rockymoo

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. tcl_session1 tcl_session1 Public

    1

  2. synthosphere synthosphere Public

    yosys

    Verilog

  3. 25day-challenge- 25day-challenge- Public

  4. amba_apb_simple-bus-architecture-design-using-verilog- amba_apb_simple-bus-architecture-design-using-verilog- Public

    This project involved designing and implementing an APB bus controller using Verilog. The controller efficiently manages data transfers between a master and multiple slave devices, adhering to the …