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Merged
rp15 merged 12 commits into from
Jan 7, 2026
Merged

Scratch/cgra_fir_vector_global_reduce #1

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54356c4
[PyMTL output] Adding generated RTL and tb files.
rp15 Jan 3, 2026
aa1d184
[Vector FU] Ensuring the whole signal is assigned to avoid xprop in SV.
rp15 Jan 6, 2026
a57fdfa
[PyMTL output] Adding generated RTL file with init fixes.
rp15 Jan 6, 2026
95b5edf
[SV tb] Adding hand-coded tb.
rp15 Jan 3, 2026
730cb5e
[PyMTL SV tb] Remove x-chk fail.
rp15 Jan 6, 2026
9cf56ed
[SV tb] Add real cfg vectors and updated CGRA RTL instantiation, data…
rp15 Jan 6, 2026
8be2120
[SV tb] Packing-function header for the new CGRA RTL.
rp15 Jan 6, 2026
106824d
[SV tb] Update CGRA instance name.
rp15 Jan 6, 2026
3d274a9
[SV tb] Update run cmds.
rp15 Jan 6, 2026
6efba6b
Revert "[PyMTL output] Adding generated RTL file with init fixes."
rp15 Jan 6, 2026
8a4b346
Revert "[PyMTL SV tb] Remove x-chk fail."
rp15 Jan 6, 2026
7eeb4a1
Revert "[PyMTL output] Adding generated RTL and tb files."
rp15 Jan 6, 2026
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1 change: 1 addition & 0 deletions fu/vector/VectorAllReduceRTL.py
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Original file line number Diff line number Diff line change
Expand Up @@ -90,6 +90,7 @@ def construct(s, DataType, CtrlType,
high = (i + 1) * sub_bw
# s.connect() works with slice objects directly during elaboration.
s.temp_result[i][0:sub_bw] //= s.recv_in[0].msg.payload[low:high]
s.temp_result[i][sub_bw:data_bitwidth] //= 0

@update
def update_result():
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4 changes: 2 additions & 2 deletions fu/vector/VectorMulComboRTL.py
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Expand Up @@ -95,8 +95,8 @@ def update_input_output():

for i in range(num_lanes):
s.temp_result[i] @= TempDataType(0)
s.Fu[i].recv_in[0].msg[0:sub_bw] @= FuDataType()
s.Fu[i].recv_in[1].msg[0:sub_bw] @= FuDataType()
s.Fu[i].recv_in[0].msg @= 0
s.Fu[i].recv_in[1].msg @= 0

if s.recv_opt.msg.operation == OPT_VEC_MUL:
# Connection: split into vectorized FUs
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1 change: 1 addition & 0 deletions multi_cgra/test/sv_test/MeshMultiCgraRTL_2x2_fir_scalar_tb.v
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Expand Up @@ -3,6 +3,7 @@
`include "header.sv"

// vcs -sverilog -full64 -timescale=1ns/1ps ../MeshMultiCgraRTL__explicit__pickled.v MeshMultiCgraRTL_2x2_fir_scalar_tb.v -debug_access+all
// vcs -sverilog -full64 -timescale=1ns/1ps ../../../../../coredec_acc_soc/accelerator_soc/MeshMultiCgraRTL__explicit__pickled.v ../MeshMultiCgraRTL_2x2_fir_scalar_tb.v -debug_access+all +incdir+..

module cgra_test
(
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