accelerator_soc

VectorCGRA and RISC-V CPU integration.

Name		Name	Last commit message	Last commit date
Latest commit History 78 Commits
.github/workflows		.github/workflows
VectorCGRA @ 2d40b3a		VectorCGRA @ 2d40b3a
axi @ d74943c		axi @ d74943c
common_cells @ 1d5c6fc		common_cells @ 1d5c6fc
erv_RISC-V @ 9ea53b2		erv_RISC-V @ 9ea53b2
src		src
src_fir_vector		src_fir_vector
sw		sw
verif		verif
verif_fir_vector		verif_fir_vector
.gitignore		.gitignore
.gitmodules		.gitmodules
README.md		README.md

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