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manim-digital
manim-digital PublicA Manim library that implements combinational and sequential digital logic components.
Python 1
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FPGA-UART-ALU
FPGA-UART-ALU PublicForked from sifferman/verilog_template
This project implements an FPGA ALU that can perform 32-bit addition, multiplication, and division over UART.
SystemVerilog
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vivaldi
vivaldi PublicA mini FPGA synthesizer built for the Nexys Video Artix-7 FPGA from Digilent.
Tcl
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