Basic inline assembly support for SPARC and SPARC64 #132472

taiki-e · 2024-11-01T19:18:53Z

This implements asm_experimental_arch (tracking issue #93335) for SPARC and SPARC64.

This PR includes:

General-purpose registers r[0-31] (reg register class, LLVM/GCC constraint r)
Supported types: i8, i16, i32, i64 (SPARC64-only)
Aliases: g[0-7] (r[0-7]), o[0-7] (r[8-15]), l[0-7] (r[16-23]), i[0-7] (r[24-31])
y register (clobber-only, needed for clobber_abi)
preserves_flags: Integer condition codes (icc, xcc) and floating-point condition codes (fcc*)

The following are not included:

64-bit integer support on SPARC-V8+'s global or out registers (g[0-7], o[0-7]): GCC's h constraint (it seems that there is no corresponding constraint in LLVM?)
Floating-point registers (LLVM/GCC constraint e/f):
I initially tried to implement this, but postponed it for now because there seemed to be several parts in LLVM that behaved differently than in the LangRef's description.
clobber_abi: Support for floating-point registers is needed.

Refs:

LLVM
- Reserved registers https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp#L52
- Register definitions https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/Sparc/SparcRegisterInfo.td
- Supported constraints https://llvm.org/docs/LangRef.html#supported-constraint-code-list
GCC
- Reserved registers https://github.com/gcc-mirror/gcc/blob/63b6967b06b5387821c4e5f2c113da6aaeeae2b7/gcc/config/sparc/sparc.h#L633-L658
- Supported constraints https://gcc.gnu.org/onlinedocs/gcc/Machine-Constraints.html
SPARC ISA/ABI
- (64-bit ISA) The SPARC Architecture Manual, Version 9
  (32-bit ISA) The SPARC Architecture Manual, Version 8
  (64-bit ABI) System V Application Binary Interface SPARC Version 9 Processor Supplement, Rev 1.35
  (32-bit ABI) System V Application Binary Interface SPARC Processor Supplement, Third Edition
  The above docs can be downloaded from https://sparc.org/technical-documents
- (32-bit V8+ ABI) The V8+ Technical Specification
  https://temlib.org/pub/SparcStation/Standards/V8plus.pdf

cc @thejpster (sparc-unknown-none-elf target maintainer)
(AFAIK, other sparc/sprac64 targets don't have target maintainers)

r? @Amanieu

@rustbot label +O-SPARC +A-inline-assembly

rustbot · 2024-11-01T19:19:03Z

Some changes occurred in compiler/rustc_codegen_gcc

cc @antoyo, @GuillaumeGomez

taiki-e · 2024-11-01T19:24:36Z

compiler/rustc_target/src/asm/sparc.rs

+pub(crate) fn is_v7_or_v8(arch: InlineAsmArch, target: &Target) -> bool {
+    // FIXME: There are any number of CPUs that imply SPARC-V8+, and checking the cpu
+    // string in the target specs is not the ideal approach here, but there
+    // doesn't seem to be another good way to do this yet (https://github.com/rust-lang/rust/pull/131222).
+    // However, in LLVM 20, feature "+v8plus" will be available for this:
+    // https://github.com/llvm/llvm-project/commit/aca971d336d9c7650120fc0fd6dfe58866408216
+    arch == InlineAsmArch::Sparc && target.options.cpu != "v9"
+}


cc #131222

UPDATE: latest version of this PR uses the target feature based approach #132472 (comment)

Perhaps adding the v9 target feature and referencing it (and after LLVM 20, adding and referencing the v8plus target feature instead of v9.) would be a good idea?
https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/Sparc/Sparc.td#L35

Implemented the target feature based approach in 14f6234.

taiki-e · 2024-11-01T19:52:23Z

/checkout/tests/ui/asm/bad-arch.rs: revision [unspecified] should specify needs-llvm-components: as it has --target set

Hmm, but when I set needs-llvm-components, I got:

/checkout/tests/ui/asm/bad-arch.rs: revision [unspecified] specifies unknown LLVM component xtensa

IIUC, it seems difficult to retain this test since there is no builtin target other than xtensa that does not support inline assembly in rust-lang/rust after this PR, and xtensa can probably support inline assembly in LLVM 20 (llvm/llvm-project@dc2d0d5, inline assembly itself is already supported in esp-rs fork).

UPDATE: removed this test

bors · 2024-11-05T19:51:55Z

☔ The latest upstream changes (presumably #129884) made this pull request unmergeable. Please resolve the merge conflicts.

Amanieu · 2024-11-06T22:40:25Z

src/doc/unstable-book/src/language-features/asm-experimental-arch.md

+| SPARC        | `r0`/`g0`                               | This is always zero and cannot be used as inputs or outputs. |
+| SPARC        | `r1`/`g1`                               | Used internally by LLVM. |
+| SPARC        | `r6`/`g6`, `r7`/`g7`                    | Reserved for system. |
+| SPARC        | `r31`/`i7`                              | Return address cannot be used as inputs or outputs. |


i6/o6 also need to be added to the list of stack/frame pointers.

And g5 needs to be mentioned as reserved on sparc32.

Amanieu · 2024-11-06T22:41:42Z

compiler/rustc_target/src/asm/sparc.rs

+    ) -> &'static [(InlineAsmType, Option<Symbol>)] {
+        match self {
+            Self::reg => {
+                // FIXME: i64 is ok for g*/o* registers on SPARC-V8+ ("h" constraint in GCC)


This is better expressed as "v9": I64 in the macro. The feature name can later be changed to v8plus.

Amanieu · 2024-11-06T22:43:01Z

compiler/rustc_target/src/asm/sparc.rs

+    _target: &Target,
+    _is_clobber: bool,
+) -> Result<(), &'static str> {
+    if is_v7_or_v8(arch, target_features) {


The condition used in LLVM is Subtarget.is64Bit(), not whether v8plus is supported. So this should check for InlineAsmArch::Sparc64 instead.

rustbot assigned Amanieu Nov 1, 2024

rustbot added S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. T-compiler Relevant to the compiler team, which will review and decide on the PR/issue. labels Nov 1, 2024

rustbot added A-inline-assembly Area: Inline assembly (`asm!(…)`) O-SPARC Target: SPARC processors labels Nov 1, 2024

taiki-e mentioned this pull request Nov 1, 2024

Tracking Issue for asm_experimental_arch #93335

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taiki-e mentioned this pull request Nov 1, 2024

Support SPARC and SPARC64 (experimental) taiki-e/atomic-maybe-uninit#31

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taiki-e added 2 commits November 3, 2024 01:08

Basic inline assembly support for SPARC and SPARC64

f49d39d

Refer target feature instead of target cpu

58769e6

taiki-e force-pushed the sparc-asm branch from 69e1e34 to 58769e6 Compare November 2, 2024 16:09

This was referenced Nov 3, 2024

Support clobber_abi in AVR inline assembly #131323

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Add v9 and leoncasa target feature to sparc #132552

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Generate correct symbols.o for sparc-unknown-none-elf #131222

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Amanieu reviewed Nov 6, 2024

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Basic inline assembly support for SPARC and SPARC64 #132472

Basic inline assembly support for SPARC and SPARC64 #132472

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Basic inline assembly support for SPARC and SPARC64 #132472

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