AVX512FP16 Part 0: Add the types

Added the `__m128h`, `__m256h`, `__m512h` and the associated `core_arch::simd` types. Started on some intrinsics

crates/core_arch/missing-x86.md

@@ -255,9 +255,6 @@
   * [ ] [`_mm256_castsi256_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castsi256_ph)
   * [ ] [`_mm256_cvtsh_h`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtsh_h)
   * [ ] [`_mm256_set1_pch`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set1_pch)
-  * [ ] [`_mm256_set1_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set1_ph)
-  * [ ] [`_mm256_set_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set_ph)
-  * [ ] [`_mm256_setr_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setr_ph)
   * [ ] [`_mm256_zextph128_ph256`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_zextph128_ph256)
   * [ ] [`_mm512_abs_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_abs_ph)
   * [ ] [`_mm512_add_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_add_ph)
@@ -584,10 +581,6 @@
   * [ ] [`_mm512_scalef_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_scalef_ph)
   * [ ] [`_mm512_scalef_round_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_scalef_round_ph)
   * [ ] [`_mm512_set1_pch`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set1_pch)
-  * [ ] [`_mm512_set1_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set1_ph)
-  * [ ] [`_mm512_set_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set_ph)
-  * [ ] [`_mm512_setr_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setr_ph)
-  * [ ] [`_mm512_setzero_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setzero_ph)
   * [ ] [`_mm512_sqrt_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sqrt_ph)
   * [ ] [`_mm512_sqrt_round_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_sqrt_round_ph)
   * [ ] [`_mm512_store_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_store_ph)
@@ -810,10 +803,6 @@
   * [ ] [`_mm_scalef_round_sh`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_scalef_round_sh)
   * [ ] [`_mm_scalef_sh`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_scalef_sh)
   * [ ] [`_mm_set1_pch`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set1_pch)
-  * [ ] [`_mm_set1_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set1_ph)
-  * [ ] [`_mm_set_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set_ph)
-  * [ ] [`_mm_set_sh`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set_sh)
-  * [ ] [`_mm_setr_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_setr_ph)
   * [ ] [`_mm_sqrt_round_sh`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sqrt_round_sh)
   * [ ] [`_mm_sqrt_sh`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sqrt_sh)
   * [ ] [`_mm_store_sh`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_store_sh)
@@ -997,7 +986,6 @@
   * [ ] [`_mm256_roundscale_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_roundscale_ph)
   * [ ] [`_mm256_rsqrt_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_rsqrt_ph)
   * [ ] [`_mm256_scalef_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_scalef_ph)
-  * [ ] [`_mm256_setzero_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setzero_ph)
   * [ ] [`_mm256_sqrt_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_sqrt_ph)
   * [ ] [`_mm256_store_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_store_ph)
   * [ ] [`_mm256_storeu_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_storeu_ph)
@@ -1182,7 +1170,6 @@
   * [ ] [`_mm_roundscale_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_roundscale_ph)
   * [ ] [`_mm_rsqrt_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_rsqrt_ph)
   * [ ] [`_mm_scalef_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_scalef_ph)
-  * [ ] [`_mm_setzero_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_setzero_ph)
   * [ ] [`_mm_sqrt_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sqrt_ph)
   * [ ] [`_mm_store_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_store_ph)
   * [ ] [`_mm_storeu_ph`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_storeu_ph)

crates/core_arch/src/lib.rs

@@ -33,7 +33,8 @@
     asm_const,
     target_feature_11,
     generic_arg_infer,
-    asm_experimental_arch
+    asm_experimental_arch,
+    f16
 )]
 #![cfg_attr(test, feature(test, abi_vectorcall, stdarch_internal))]
 #![deny(clippy::missing_inline_in_public_items)]

crates/core_arch/src/simd.rs

@@ -3,9 +3,10 @@
 #![allow(non_camel_case_types)]
 
 macro_rules! simd_ty {
-    ($id:ident [$ety:ident]: $($elem_name:ident),*) => {
+    ($(#[$stability:meta])? $id:ident [$ety:ident]: $($elem_name:ident),*) => {
         #[repr(simd)]
         #[derive(Copy, Clone, Debug, PartialEq)]
+        $(#[$stability])?
         pub(crate) struct $id { $(pub $elem_name: $ety),* }
 
         #[allow(clippy::use_self)]
@@ -186,9 +187,20 @@ simd_ty!(
 simd_ty!(i32x4[i32]: x0, x1, x2, x3);
 simd_ty!(i64x2[i64]: x0, x1);
 
+simd_ty!(
+    #[unstable(feature = "f16", issue = "116909")]
+    f16x8[f16]:
+    x0,
+    x1,
+    x2,
+    x3,
+    x4,
+    x5,
+    x6,
+    x7
+);
 simd_ty!(f32x4[f32]: x0, x1, x2, x3);
 simd_ty!(f64x2[f64]: x0, x1);
-simd_ty!(f64x4[f64]: x0, x1, x2, x3);
 
 simd_m_ty!(
     m8x16[i8]:
@@ -359,6 +371,26 @@ simd_ty!(
 );
 simd_ty!(i64x4[i64]: x0, x1, x2, x3);
 
+simd_ty!(
+    #[unstable(feature = "f16", issue = "116909")]
+    f16x16[f16]:
+    x0,
+    x1,
+    x2,
+    x3,
+    x4,
+    x5,
+    x6,
+    x7,
+    x8,
+    x9,
+    x10,
+    x11,
+    x12,
+    x13,
+    x14,
+    x15
+);
 simd_ty!(
     f32x8[f32]:
     x0,
@@ -370,6 +402,7 @@ simd_ty!(
     x6,
     x7
 );
+simd_ty!(f64x4[f64]: x0, x1, x2, x3);
 
 simd_m_ty!(
     m8x32[i8]:
@@ -688,6 +721,42 @@ simd_ty!(
     x15
 );
 
+simd_ty!(
+    #[unstable(feature = "f16", issue = "116909")]
+    f16x32[f16]:
+    x0,
+    x1,
+    x2,
+    x3,
+    x4,
+    x5,
+    x6,
+    x7,
+    x8,
+    x9,
+    x10,
+    x11,
+    x12,
+    x13,
+    x14,
+    x15,
+    x16,
+    x17,
+    x18,
+    x19,
+    x20,
+    x21,
+    x22,
+    x23,
+    x24,
+    x25,
+    x26,
+    x27,
+    x28,
+    x29,
+    x30,
+    x31
+);
 simd_ty!(
     f32x16[f32]:
     x0,