RISC-V Processor

A comprehensive RISC-V processor implementation in Verilog featuring multiple processor variants, a 5-stage pipeline, and extensive testing framework.

Features

• 5-Stage Pipelined RISC-V Core with full forwarding logic
• Multiple Processor Variants: stalling, bypass, and long pipeline implementations
• Integer Multiply/Divide Unit with iterative algorithms
• Comprehensive Test Suite including assembly tests and benchmarks
• VCD Waveform Generation for debugging and analysis

Quick Start

Prerequisites

• Icarus Verilog (iverilog) compiler
• Make build system
• Perl (for test result parsing)

Building

cd build
make                    # Build all executables
make check             # Run all unit tests

Running Tests

# Run assembly tests on the long pipeline variant
make check-asm-riscvlong

# Run benchmarks
make run-bmark-riscvlong

# Run individual test with VCD output
./riscvlong-sim +stats=1 +vcd=1 +exe=riscv-add.vmh

Architecture

Processor Variants

• riscvlong: 5-stage pipelined processor with full forwarding (recommended)
• riscvstall: Processor that stalls on hazards
• riscvbyp: Processor with basic bypass logic

Core Components

• Control Unit: Instruction decode and pipeline control
• Datapath: 5-stage pipeline with ALU, register file, and forwarding
• Multiply/Divide Unit: Pipelined integer arithmetic operations
• Memory Interface: Instruction and data memory ports

Test Suite

The project includes extensive testing:

• 87 Assembly Tests: Individual RISC-V instruction verification
• 4 Benchmarks: Performance evaluation programs
• Unit Tests: Module-level verification
• Random Delay Testing: Memory timing variation testing

Project Structure

├── build/          # Build system and executables
├── imuldiv/        # Multiply/divide unit implementation
├── riscvlong/      # 5-stage pipelined processor
├── tests/          # Assembly test sources
└── ubmark/         # Benchmark sources

Supported Instructions

• Arithmetic: ADD, SUB, MUL, DIV, REM (signed/unsigned)
• Logical: AND, OR, XOR, shifts (SLL, SRL, SRA)
• Immediate: ADDI, ANDI, ORI, XORI, SLLI, SRLI, SRAI
• Memory: LW, LH, LB, SW, SH, SB (with signed/unsigned variants)
• Branches: BEQ, BNE, BLT, BGE, BLTU, BGEU
• Jumps: JAL, JALR
• Compare: SLT, SLTU, SLTI, SLTIU
• Upper Immediate: LUI

Architecture Details

5-Stage Pipeline

The riscvlong processor implements a classic 5-stage RISC pipeline:

1. Fetch (F): Instruction fetch from memory
2. Decode (D): Instruction decode and register file read
3. Execute (X): ALU operations and address calculation
4. Memory (M): Data memory access
5. Writeback (W): Register file write

Forwarding and Hazard Handling

• Data Forwarding: Full forwarding network to eliminate data hazards
• Control Hazards: Branch prediction and pipeline flushing
• Memory Hazards: Pipeline stalling for memory dependencies

Core Modules

• riscvlong-Core.v: Top-level integration of control and datapath
• riscvlong-CoreCtrl.v: Pipeline control, instruction decode, and hazard detection
• riscvlong-CoreDpath.v: Complete datapath with forwarding logic
• riscvlong-CoreDpathAlu.v: 32-bit ALU supporting all RISC-V operations
• riscvlong-CoreDpathRegfile.v: 32-register file with dual read ports
• riscvlong-CoreDpathPipeMulDiv.v: Pipelined multiply/divide unit

Memory Interface

• Instruction Memory: 32-bit address, 32-bit data interface
• Data Memory: 32-bit address, 32-bit data with byte/halfword/word access
• Memory Request/Response: Standardized message format with ready/valid handshaking

Testing Procedures

Unit Testing

Each module includes comprehensive unit tests (.t.v files):

• Module-level verification with directed test vectors
• Self-checking testbenches with pass/fail reporting
• Coverage of corner cases and error conditions

Assembly Testing

Individual instruction verification:

• 87 assembly tests covering all supported RISC-V instructions
• Tests run on all processor variants for comparison
• Both normal and random-delay execution modes
• Automatic pass/fail detection and reporting

Benchmark Testing

Performance evaluation with realistic programs:

• Vector-vector add (ubmark-vvadd.vmh)
• Complex multiplication (ubmark-cmplx-mult.vmh)
• Masked filter (ubmark-masked-filter.vmh)
• Binary search (ubmark-bin-search.vmh)

Debugging Support

• VCD Generation: Waveform output for signal analysis
• Statistics Mode: Cycle counts and performance metrics
• Verbose Output: Detailed execution tracing
• Random Delays: Memory timing variation testing