IITB-RISC

Design a 6-stage pipelined processor, IITB-RISC-23, whose instruction set architecture is provided. IITB-RISC is a 16-bit very simple computer developed for teaching based on the Little Computer Architecture. The IITB-RISC-23 is a 16-bit computer system with 8 registers. It should follow the standard 6-stage pipelines (Instruction fetch, instruction decode, register read, execute, memory access, and write back). The architecture should be optimized for performance, i.e., should include hazard mitigation techniques. Hence, it should have implemented a forwarding mechanism. Implementation of the branch predictor is optional. Group: Group of FOUR