update README

README.md

@@ -7,45 +7,45 @@
 
 RISC-V Atom is an open-source soft-core processor platform targeted for FPGAs. It is complete hardware prototyping and software development environment based around **Atom**, which is a 32-bit embedded-class processor based on the [RISC-V](https://riscv.org/) Instruction Set Architecture (ISA). 
 
-Key highlights of Atom are listed below:
-
-- Implements RV32I + *M(optional) ISA as defined in the [RISC-V unprivileged ISA manual](https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf).
+Key highlights of the RISC-V Atom projects are are listed below:
 
+- Atom processor implements `RV32I_Zicsr` ISA as defined in the [RISC-V unprivileged ISA manual](https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf).
 - Simple 2-stage pipelined architecture, ideal for smaller FPGAs.
-
 - Wishbone ready CPU interface.
-
-- Interactive RTL simulator AtomSim.
-
+- Support for RISC-V interrupts and exceptions.
+- Interactive RTL simulator - **AtomSim**.
+- In-house verification framework - **SCAR**.
+- FPGA-ready SoC implementation - **HydrogenSoC**.
+- Tiny libc like standard library - **libcatom**.
 - Wide range of example programs.
-
 - Open source under [MIT License](https://en.wikipedia.org/wiki/MIT_License).  
 
-*To be added soon
 
-***To checkout this project, Please refer to the [Getting Started Guide](https://riscv-atom.readthedocs.io/en/latest/pages/getting-started/riscv-atom.html)***:
+> ***To checkout this project, Please refer to the [Getting Started Guide](https://riscv-atom.readthedocs.io/en/latest/pages/getting-started/riscv-atom.html)***:
 
 
 ## Directory Structure
 
-- `docs` : RISCV-Atom documentation: [readthedocs](https://riscv-atom.readthedocs.io/en/latest/index.html).
+- `docs` : RISCV-Atom documentation: ([readthedocs](https://riscv-atom.readthedocs.io/en/latest/index.html))
 
 - `rtl` : Verilog sources.
   - `core` : RISCV-Atom core components.
   - `uncore` : RISCV-Atom non-core components (peripherals).
   - `dpi` : SystemVerilog DPI sources.
+  - `soc` :  SoC implementations
+  - `tb` : Testbenches
 
 - `scripts` : utility scripts.
 
 - `sim` : Atomsim source code.
   - `build` : Atomsim build files (autogenerated).
   - `docs` : Doxygen Documentation for Atomsim source code.
   - `include` : external libraries for atomsim.
-  - `run` : Atomsim runtime files like hexdumps, vcd traces etc. (autogenerated)
 
 - `sw` : RISCV-Atom software sources
+  - `bootloader` :  RISC-V Atom bootloader.
   - `examples` : RISCV-Atom examples
-  - `lib` : libc for RISCV-Atom *(libcatom)*
+  - `lib` : libc for RISCV-Atom
     - `include` : libcatom headers
     - `libcatom` : libcatom sources
     - `link` : RISC-V Atom linker scripts
@@ -64,15 +64,17 @@ Key highlights of Atom are listed below:
 
 ## Useful Links
 1. [Project Website](https://sites.google.com/view/saurabh-singh-web/projects/risc-v-atom?authuser=0)
-2. [Getting Started Guide](https://riscv-atom.readthedocs.io/en/latest/pages/getting-started/prerequisites.html)
-3. [Examples Guide](https://riscv-atom.readthedocs.io/en/latest/pages/getting-started/examples.html)
-4. [Project Documentation](https://riscv-atom.readthedocs.io/en/latest/index.html)
-<!-- 5. AtomSim Source Documentation -->
+2. [Project Documentation](https://riscv-atom.readthedocs.io/en/latest/index.html)
+    - [Getting Started Guide](https://riscv-atom.readthedocs.io/en/latest/pages/getting-started/prerequisites.html)
+    - [Examples Guide](https://riscv-atom.readthedocs.io/en/latest/pages/getting-started/examples.html)
+
 
+<!-- 5. AtomSim Source Documentation -->
 
+<!--
 ## Other related projects
 1. **AtomShell**: A simple shell for RISC-V Atom based SoCs : [AtomShell Github](https://github.com/saurabhsingh99100/atomshell)
-
+-->
 
 ## License
 This project is open-source under [MIT license](https://github.com/saursin/riscv-atom/blob/main/LICENSE)!