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rtl: wb crossbar gen minor update
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saursin committed Oct 21, 2023
1 parent 6920f5d commit 29b1f97
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Showing 2 changed files with 12 additions and 58 deletions.
39 changes: 7 additions & 32 deletions rtl/uncore/wishbone/Crossbar5_wb.v
Original file line number Diff line number Diff line change
Expand Up @@ -183,38 +183,13 @@ module Crossbar5_wb #(
endcase
end

/*
=== Stb muxing ===
In order to initiate a transaction, the master must set the cyc & stb signal of the
device with which it wants to communicate. Setting stb & cyc signals of appropriate
device depending on the selected device is handled by the interconnect
logic.
*/
always @(*) begin /* COMBINATORIAL */
// Defaults
wbm0_stb_o = 1'b0;
wbm1_stb_o = 1'b0;
wbm2_stb_o = 1'b0;
wbm3_stb_o = 1'b0;
wbm4_stb_o = 1'b0;

case(selected_device)
DEVICE_0: wbm0_stb_o = wbs_stb_i;
DEVICE_1: wbm1_stb_o = wbs_stb_i;
DEVICE_2: wbm2_stb_o = wbs_stb_i;
DEVICE_3: wbm3_stb_o = wbs_stb_i;
DEVICE_4: wbm4_stb_o = wbs_stb_i;

default: begin
wbm0_stb_o = 1'b0;
wbm1_stb_o = 1'b0;
wbm2_stb_o = 1'b0;
wbm3_stb_o = 1'b0;
wbm4_stb_o = 1'b0;
end
endcase
end

// Stb Out
assign wbm0_stb_o = wbm0_cyc_o & wbs_stb_i;
assign wbm1_stb_o = wbm1_cyc_o & wbs_stb_i;
assign wbm2_stb_o = wbm2_cyc_o & wbs_stb_i;
assign wbm3_stb_o = wbm3_cyc_o & wbs_stb_i;
assign wbm4_stb_o = wbm4_cyc_o & wbs_stb_i;

// ACK Out
assign wbs_ack_o = wbm0_ack_i
| wbm1_ack_i
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31 changes: 5 additions & 26 deletions rtl/uncore/wishbone/wb_crossbar_gen.py
Original file line number Diff line number Diff line change
Expand Up @@ -152,32 +152,11 @@ def generate(nslaves=2, name=None, output=None):
endcase
end
/*
=== Stb muxing ===
In order to initiate a transaction, the master must set the cyc & stb signal of the
device with which it wants to communicate. Setting stb & cyc signals of appropriate
device depending on the selected device is handled by the interconnect
logic.
*/
always @(*) begin /* COMBINATORIAL */
// Defaults
{%- for p in nslaves %}
wbm{{p}}_stb_o = 1'b0;
{%- endfor %}
case(selected_device)
{%- for p in nslaves %}
DEVICE_{{p}}: wbm{{p}}_stb_o = wbs_stb_i;
{%- endfor %}
default: begin
{%- for p in nslaves %}
wbm{{p}}_stb_o = 1'b0;
{%- endfor %}
end
endcase
end
// Stb Out
{%- for p in nslaves %}
assign wbm{{p}}_stb_o = wbm{{p}}_cyc_o & wbs_stb_i;
{%- endfor %}
// ACK Out
assign wbs_ack_o = {%- for p in nslaves %}
{%- if p != 0 %}
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