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remove config.mk
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- sourceme script defines VERILATOR_PATH which is used by makefile
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saursin committed Sep 7, 2023
1 parent c3cc56b commit d3bfd0f
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Showing 3 changed files with 33 additions and 16 deletions.
4 changes: 0 additions & 4 deletions config.mk

This file was deleted.

15 changes: 9 additions & 6 deletions sim/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,6 @@ RUN_DIR := run
# make directories during makefile-parse
$(shell mkdir -p $(OBJ_DIR) $(VERILATED_DIR) $(BIN_DIR) $(DEPDIR) $(RUN_DIR))

include ../config.mk
####################################################
# Verilog Configs

Expand All @@ -43,8 +42,9 @@ VFLAGS += -I$(RTL_DIR) -I$(RTL_DIR)/common -I$(RTL_DIR)/core
VFLAGS += --Mdir $(VERILATED_DIR)

# check verilator include directory
VERILATOR_INCLUDE_PATH=$(VERILATOR_PATH)/share/verilator/include
ifeq ("$(wildcard $(VERILATOR_INCLUDE_PATH)/verilated_vcd_c.cpp)","")
$(error Verilator include path invalid; Set correct Verilator include path in sim/Makefile)
$(error Verilator include path invalid)
endif

# Core files
Expand Down Expand Up @@ -214,12 +214,15 @@ $(DEPDIR)/%.Td: ;


####################################################
# Cleanup & Util Recepies
# Util & Cleanup Recepies

.PHONY: preprocess_verilog #t Preprocess verilog and dump output into a single verilog file
preprocess_verilog: $(VTOPMODULE_FILE) $(VSRCS)
$(VC) $(VFLAGS) -E $^ > verilog_dump.v
.PHONY: preprocess_verilog
preprocess_verilog: $(VTOPMODULE_FILE) $(VSRCS) #t Preprocess verilog and dump output into a single verilog file
$(VC) $(VFLAGS) -E $^ > $(soctarget)_dump.v

.PHONY: lint_verilog
lint_verilog: $(VTOPMODULE_FILE) $(VSRCS) #t Lint-check verilog code
$(VC) $(VFLAGS) --lint-only $^

.PHONY: clean
clean: #t Clean build files
Expand Down
30 changes: 24 additions & 6 deletions sourceme
Original file line number Diff line number Diff line change
@@ -1,16 +1,34 @@
## RISCV-ATOM Environment Variabes
########## RISCV-ATOM Environment Setup ##########

# export RVATOM variable (get dir containing this sourceme file)
# Uncomment if using environment modules
# module load verilator/5.006
# module load riscv64-multilib-gcc
# module load openfpgaloader

echo "> Setting environment variables..."

# RVATOM variable: points to root of riscv-atom directory (get dir containing this sourceme file)
export RVATOM=$(dirname -- "$(readlink -f "${BASH_SOURCE}")")

# VERILATOR_PATH: points to verilator installation
if command -v "verilator" &>/dev/null; then
# get verilator path
VLP=$(dirname $(dirname `which verilator`))
echo "Found Verilator at: $VLP"
export VERILATOR_PATH=$VLP
else
echo "ERROR: Verilator not found; please install verilator"
fi

# export RVATOM_LIB variable
export RVATOM_LIB="$RVATOM/sw/lib"
# export RVATOM_LIB="$RVATOM/sw/lib"

# add atomsim to path ($RVATOM/sim/build/bin)
export PATH="$RVATOM/sim/build/bin:$PATH"
# export PATH="$RVATOM/sim/build/bin:$PATH"

# add elfdump to path ($RVATOM/tools/elfdump/bin)
export PATH="$RVATOM/tools/elfdump/bin:$PATH"
# export PATH="$RVATOM/tools/elfdump/bin:$PATH"

# add $RVATOM/scripts to path
export PATH="$RVATOM/scripts:$PATH"
# export PATH="$RVATOM/scripts:$PATH"

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