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Update bootloader; Refactor & cleanup
- Bootloader: - rename: flashboot -> bootloader - add bootmode functionality - rtl/tb testbench: - update testbench - add makefile - minor refactoring & cleanup
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Original file line number | Diff line number | Diff line change |
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@@ -1,49 +1,59 @@ | ||
`default_nettype none | ||
`timescale 1ns/1ps | ||
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`include "../HydrogenSoC_Config.vh" | ||
`include "HydrogenSoC_Config.vh" | ||
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module isim_tb; | ||
reg clk_i = 0; | ||
reg rst_i = 1; | ||
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wire [`NGPIO-1:0] gpio_io; | ||
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// UART | ||
reg uart_usb_rx_i = 0; | ||
wire uart_usb_tx_o; | ||
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reg uart_io_rx_i = 0; | ||
wire uart_io_tx_o; | ||
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// UART MUX | ||
reg uart_mux_sel = 0; | ||
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// TEST POINTS | ||
wire uart_rx_test_point_o; | ||
wire uart_tx_test_point_o; | ||
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HydrogenSoC hsoc ( | ||
clk_i, | ||
rst_i, | ||
gpio_io, | ||
uart_usb_rx_i, | ||
uart_usb_tx_o, | ||
uart_io_rx_i, | ||
uart_io_tx_o, | ||
uart_mux_sel, | ||
uart_rx_test_point_o, | ||
uart_tx_test_point_o | ||
); | ||
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initial begin | ||
#10; | ||
rst_i = 0; | ||
end | ||
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always begin | ||
#1; | ||
clk_i <= ~clk_i; | ||
end | ||
reg clk_i = 0; | ||
reg rst_i = 1; | ||
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// GPIO | ||
wire [`NGPIO-1:0] gpio_io; | ||
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// UART | ||
reg uart_mux_sel_i = 0; | ||
reg uart_usb_rx_i = 0; | ||
wire uart_usb_tx_o; | ||
reg uart_io_rx_i = 0; | ||
wire uart_io_tx_o; | ||
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// SPI | ||
reg spi_miso_i = 0; | ||
wire spi_mosi_o; | ||
wire spi_sck_o; | ||
wire spi_cs_o; | ||
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// DUT | ||
HydrogenSoC hosc( | ||
clk_i, | ||
rst_i, | ||
gpio_io, | ||
uart_mux_sel_i, | ||
uart_usb_rx_i, | ||
uart_usb_tx_o, | ||
uart_io_rx_i, | ||
uart_io_tx_o, | ||
spi_miso_i, | ||
spi_mosi_o, | ||
spi_sck_o, | ||
spi_cs_o | ||
); | ||
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initial begin | ||
$dumpfile("trace.vcd"); | ||
$dumpvars(0, isim_tb); | ||
#10; | ||
rst_i = 0; | ||
end | ||
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reg [63:0] clk_ctr = 0; | ||
always @(posedge clk_i) begin | ||
clk_ctr <= clk_ctr + 1; | ||
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if(clk_ctr == 200000) | ||
$finish(0); | ||
end | ||
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always begin | ||
#1; clk_i <= ~clk_i; | ||
end | ||
endmodule |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,39 @@ | ||
rtl_dir = $(RVATOM)/rtl | ||
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VFLAGS = -Wall | ||
VFLAGS += -I$(RVATOM)/rtl/soc/hydrogensoc -I$(RVATOM)/rtl/common -I$(RVATOM)/rtl/core | ||
VFLAGS += -D__ROM_INIT_FILE__='"$(RVATOM)/sw/flashboot/rom.hex"' | ||
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VSRCS = $(rtl_dir)/tb/HydrogenSoC_tb.v | ||
VSRCS += $(rtl_dir)/soc/hydrogensoc/HydrogenSoC.v | ||
VSRCS += $(rtl_dir)/core/AtomRV.v | ||
VSRCS += $(rtl_dir)/core/Alu.v | ||
VSRCS += $(rtl_dir)/core/Decode.v | ||
VSRCS += $(rtl_dir)/core/RegisterFile.v | ||
VSRCS += $(rtl_dir)/core/CSR_Unit.v | ||
VSRCS += $(rtl_dir)/core/AtomRV_wb.v | ||
VSRCS += $(rtl_dir)/uncore/wishbone/Arbiter.v | ||
VSRCS += $(rtl_dir)/uncore/wishbone/Arbiter3_wb.v | ||
VSRCS += $(rtl_dir)/uncore/wishbone/Crossbar5_wb.v | ||
VSRCS += $(rtl_dir)/uncore/wishbone/Priority_encoder.v | ||
VSRCS += $(rtl_dir)/uncore/gpio/IOBuf.v | ||
VSRCS += $(rtl_dir)/uncore/gpio/GPIO.v | ||
VSRCS += $(rtl_dir)/uncore/mem/DualPortRAM_wb.v | ||
VSRCS += $(rtl_dir)/uncore/mem/SinglePortROM_wb.v | ||
VSRCS += $(rtl_dir)/uncore/mem/SinglePortRAM_wb.v | ||
VSRCS += $(rtl_dir)/uncore/uart/UART.v | ||
VSRCS += $(rtl_dir)/uncore/uart/UART_core.v | ||
VSRCS += $(rtl_dir)/uncore/spi/SPI_wb.v | ||
VSRCS += $(rtl_dir)/uncore/spi/SPI_core.v | ||
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default: trace.vcd | ||
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trace.vcd: out.vvp | ||
vvp out.vvp | ||
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out.vvp: $(VSRCS) | ||
iverilog $(VFLAGS) -o $@ $^ | ||
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.PHONY: clean | ||
clean: | ||
rm -f *.vvp *.vcd |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,4 @@ | ||
{ | ||
"BOOTROM" : ["0x00010000", "4096", "h", "rom.hex"], | ||
"BOOTRAM" : ["0x20008000", "16384", "h", "ram.hex"] | ||
} |
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Original file line number | Diff line number | Diff line change |
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@@ -1,19 +1,18 @@ | ||
EXEC:= flashboot.elf | ||
EXEC:= bootloader.elf | ||
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CFLAGS:= -mabi=ilp32 -march=rv32i -nostartfiles -ffreestanding -DTARGET_HYDROGENSOC -Os | ||
CFLAGS+= -I $(RVATOM_LIB)/include | ||
LFLAGS:= -L $(RVATOM_LIB)/ -T link_flashboot.lds -lcatom -Xlinker -Map $(EXEC).map -Wl,--gc-sections | ||
LFLAGS:= -L $(RVATOM_LIB)/ -T link_bootloader.lds -lcatom -Xlinker -Map $(EXEC).map | ||
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default: boot | ||
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.PHONY: boot | ||
boot: $(EXEC) | ||
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$(EXEC): main.c crt0.S | ||
$(EXEC): xmodem.c bootloader.c crt0.S | ||
riscv64-unknown-elf-gcc $(CFLAGS) -o $@ $^ $(LFLAGS) | ||
riscv64-unknown-elf-objdump -htd $@ > $@.objdump | ||
python3 $$RVATOM/scripts/convelf.py -t elf -j hydrogensoc.json --keep-temp $(EXEC) -c | ||
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.PHONY: clean | ||
clean: | ||
rm -f *.o *.objdump *.map *.elf *.hex | ||
rm -f *.o *.objdump *.map *.elf |
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Original file line number | Diff line number | Diff line change |
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@@ -18,6 +18,7 @@ _start: | |
# ===== Call main ===== | ||
jal main | ||
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_exit: | ||
ebreak # Exit simulation | ||
j _exit |
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