cfgparse: add support for conditionals

saursin · Nov 26, 2023 · f5ad5e9 · f5ad5e9
1 parent 47f2a22
commit f5ad5e9
Show file tree

Hide file tree

Showing 10 changed files with 125 additions and 107 deletions.
diff --git a/rtl/config/hydrogensoc.json b/rtl/config/hydrogensoc.json
@@ -1,9 +1,19 @@
 {
     "name": "hydrogensoc",
+    "params": {
+        "en_embedded": false,
+        "en_compressed": true,
+        "en_csr": true,
+        "en_exceptions": true
+    },
+    "isa": "rv32[en_embedded?e:i][en_compressed?c:]_[en_csr?zicsr:]",
+    "abi": "ilp32[en_embedded?e:]",
     "vtopmodule": "HydrogenSoC",
     "vdefines": [
-        "ENABLE_RISCV_ZICSR",
-        "ENABLE_RISCV_EXCEPTIONS"
+        "[en_embedded?EN_RVE:]",
+        "[en_csr?EN_RVZICSR:]",
+        "[en_exceptions?EN_EXCEPT:]",
+        "[en_compressed?EN_RVC:]"
     ],
     "vsrcs": [
         "${RVATOM}/rtl/soc/hydrogensoc/HydrogenSoC.v"

diff --git a/rtl/core/AtomRV.v b/rtl/core/AtomRV.v
@@ -16,10 +16,10 @@
 `default_nettype none
 
 `ifdef EN_EXCEPT
-`ifndef RV_ZICSR
+`ifndef EN_RVZICSR
 `error "Exception support requires CSR registers"
-`endif
-`endif
+`endif // EN_EXCEPT
+`endif // EN_RVZICSR
 
 
 
@@ -58,7 +58,7 @@ module AtomRV # (
 );
     wire instr_request_valid = !rst_i; // Always valid (Except on Reset condition)
 
-    `ifdef RV_C
+    `ifdef EN_RVC
     wire [31:0] rvc_aligner_fetch_addr_o;
     wire        rvc_aligner_fetch_valid_o;
 
@@ -90,12 +90,12 @@ module AtomRV # (
         .instr_o        (rvc_decdr_instr_o),
         .is_compressed  (rvc_decdr_is_compressed_o) // handle
     );
-    `endif // RV_C
+    `endif // EN_RVC
 
-    assign      iport_addr_o = `INLINE_IFDEF(RV_C, rvc_aligner_fetch_addr_o, ProgramCounter);
-    assign      iport_valid_o = `INLINE_IFDEF(RV_C, rvc_aligner_fetch_valid_o, instr_request_valid);
-    wire        iport_acknowledged = `INLINE_IFDEF(RV_C, rvc_alignr_ack_o, iport_ack_i);
-    wire [31:0] fetched_instr = `INLINE_IFDEF(RV_C, rvc_decdr_instr_o, iport_data_i);
+    assign      iport_addr_o = `INLINE_IFDEF(EN_RVC, rvc_aligner_fetch_addr_o, ProgramCounter);
+    assign      iport_valid_o = `INLINE_IFDEF(EN_RVC, rvc_aligner_fetch_valid_o, instr_request_valid);
+    wire        iport_acknowledged = `INLINE_IFDEF(EN_RVC, rvc_alignr_ack_o, iport_ack_i);
+    wire [31:0] fetched_instr = `INLINE_IFDEF(EN_RVC, rvc_decdr_instr_o, iport_data_i);
 
     /*
         ///////////// Protocol specification //////////////
@@ -199,7 +199,7 @@ module AtomRV # (
 
     `ifdef EN_EXCEPT
     // Exception signals
-    wire    except_instr_addr_misaligned = `INLINE_IFDEF(RV_C, ProgramCounter[0], |ProgramCounter[1:0]);    
+    wire    except_instr_addr_misaligned = `INLINE_IFDEF(EN_RVC, ProgramCounter[0], |ProgramCounter[1:0]);    
     wire    except_load_addr_misaligned = dport_valid_o & !dport_we_o & |dport_addr_o[1:0];
     wire    except_store_addr_misaligned = dport_valid_o & dport_we_o & |dport_addr_o[1:0];
 
@@ -216,7 +216,7 @@ module AtomRV # (
         Program Counter
     */
     reg [31:0] ProgramCounter   /*verilator public*/;
-    wire [31:0] ProgramCounter_next = ProgramCounter + `INLINE_IFDEF(RV_C, (rvc_decdr_is_compressed_o ? 32'd2 : 32'd4), 32'd4);
+    wire [31:0] ProgramCounter_next = ProgramCounter + `INLINE_IFDEF(EN_RVC, (rvc_decdr_is_compressed_o ? 32'd2 : 32'd4), 32'd4);
 
     always @(posedge clk_i) begin 
         if(rst_i)
@@ -245,14 +245,14 @@ module AtomRV # (
         initial begin
             dpi_logger_start();
         end
-    `endif
+    `endif // DPI_LOGGER
 
     `ifdef LOG_RVATOM_JUMP
     always @(posedge clk_i) begin
         if(jump_decision)
             dpi_logger("Jump  address=0x%x\n", {alu_out[31:1], 1'b0});
     end
-    `endif
+    `endif // LOG_RVATOM_JUMP
 
     //----------------------------------------------------------
     // PIPELINE REGISTERS
@@ -324,10 +324,10 @@ module AtomRV # (
     wire            d_mem_load_store;
     wire            d_mem_we;
 
-    `ifdef RV_ZICSR
+    `ifdef EN_RVZICSR
     wire    [2:0]   d_csru_op_sel;
     wire            d_csru_we;
-    `endif
+    `endif // EN_RVZICSR
 
     `ifdef EN_EXCEPT
     wire            d_trap_ret;
@@ -358,11 +358,11 @@ module AtomRV # (
         .d_mem_load_store   (d_mem_load_store),
         .mem_we_o           (d_mem_we)
 
-        `ifdef RV_ZICSR
+        `ifdef EN_RVZICSR
         ,
         .csru_op_sel_o      (d_csru_op_sel),
         .csru_we_o          (d_csru_we)
-        `endif
+        `endif // EN_RVZICSR
 
         `ifdef EN_EXCEPT
         ,
@@ -386,22 +386,22 @@ module AtomRV # (
             3'd2:   rf_rd_data = alu_out;
             3'd3:   rf_rd_data = {31'd0, comparison_result};
             3'd4:   rf_rd_data = memload;
-            `ifdef RV_ZICSR
+            `ifdef EN_RVZICSR
             3'd5:   rf_rd_data = csru_data_o;
-            `endif
+            `endif // EN_RVZICSR
 
             default: rf_rd_data = 32'd0;
         endcase
     end
 
 
-    `ifdef RV_E
+    `ifdef EN_RVE
     localparam RF_INDX_BITS = 3;
     localparam RF_NREGS = 16;
     `else
     localparam RF_INDX_BITS = 4;
     localparam RF_NREGS = 32;
-    `endif
+    `endif // EN_RVE
 
     wire    [31:0]  rf_rs1;
     wire    [31:0]  rf_rs2;
@@ -422,13 +422,13 @@ module AtomRV # (
         .Data_i     (rf_rd_data)
     );
 
-    `ifdef RV_E
+    `ifdef EN_RVE
         // We need these because we are not using MSB 
-        // of select lines in RV_E
+        // of select lines
         `UNUSED_VAR(d_rs1_sel)
         `UNUSED_VAR(d_rs2_sel)
         `UNUSED_VAR(d_rd_sel)
-    `endif
+    `endif // EN_RVE
 
 
     /*
@@ -475,7 +475,7 @@ module AtomRV # (
         endcase
     end
 
-    `ifdef RV_ZICSR
+    `ifdef EN_RVZICSR
     /*
         ////// CSR Unit //////
         Contains all the Control and status registers
@@ -525,7 +525,7 @@ module AtomRV # (
         `UNUSED_VAR(ARCH_ID)
         `UNUSED_VAR(IMPL_ID)
         `UNUSED_VAR(HART_ID)
-    `endif
+    `endif // EN_RVZICSR
 
 
     /*

diff --git a/rtl/core/CSR_Unit.v b/rtl/core/CSR_Unit.v
@@ -176,19 +176,19 @@ module CSR_Unit#
         1'b0,               // bit-15    P Tentatively reserved for Packed-SIMD extension
         1'b0,               // bit-14    O Reserved
         1'b0,               // bit-13    N Tentatively reserved for User-Level Interrupts extension
-        `isdefined(RV_M),   // bit-12    M Integer Multiply/Divide extension
+        `isdefined(EN_RVM), // bit-12    M Integer Multiply/Divide extension
         1'b0,               // bit-11    L Reserved
         1'b0,               // bit-10    K Reserved
         1'b0,               // bit-9     J Tentatively reserved for Dynamically Translated Languages extension
         1'b1,               // bit-8     I RV32I/64I/128I base ISA
         1'b0,               // bit-7     H Hypervisor extension
         1'b0,               // bit-6     G Reserved
-        `isdefined(RV_F),   // bit-5     F Single-precision floating-point extension
-        `isdefined(RV_E),   // bit-4     E RV32E base ISA
-        `isdefined(RV_D),   // bit-3     D Double-precision floating-point extension
-        `isdefined(RV_C),   // bit-2     C Compressed extension
+        `isdefined(EN_RVF), // bit-5     F Single-precision floating-point extension
+        `isdefined(EN_RVE), // bit-4     E RV32E base ISA
+        `isdefined(EN_RVD), // bit-3     D Double-precision floating-point extension
+        `isdefined(EN_RVC), // bit-2     C Compressed extension
         1'b0,               // bit-1     B Tentatively reserved for Bit-Manipulation extension
-        `isdefined(RV_A)    // bit-0     A Atomic extension
+        `isdefined(EN_RVA)  // bit-0     A Atomic extension
     };
 
 

diff --git a/rtl/core/Decode.v b/rtl/core/Decode.v
@@ -32,16 +32,16 @@ module Decode
     output  reg             d_mem_load_store,
     output  reg             mem_we_o
 
-    `ifdef RV_ZICSR
+    `ifdef EN_RVZICSR
     ,
     output  wire    [2:0]   csru_op_sel_o,
     output  reg             csru_we_o
-    `endif
+    `endif // EN_RVZICSR
 
     `ifdef EN_EXCEPT
     ,
     output  reg             trap_ret_o
-    `endif
+    `endif // EN_EXCEPT
 );
 
     // Decode fields
@@ -51,9 +51,9 @@ module Decode
 
     assign mem_access_width_o = func3;
 
-    `ifdef RV_ZICSR
+    `ifdef EN_RVZICSR
     assign csru_op_sel_o = func3;
-    `endif
+    `endif // EN_RVZICSR
 
 
     assign  rd_sel_o    = instr_i[11:7];
@@ -104,13 +104,13 @@ module Decode
         d_mem_load_store = 1'b0;
         imm_format = `RV_IMM_TYPE_U;
 
-        `ifdef RV_ZICSR
+        `ifdef EN_RVZICSR
         csru_we_o = 0;
-        `endif
+        `endif // EN_RVZICSR
 
         `ifdef EN_EXCEPT
         trap_ret_o = 1'b0;
-        `endif
+        `endif // EN_EXCEPT
 
 
         casez({func7, func3, opcode})
@@ -521,15 +521,15 @@ module Decode
                     trap_ret_o = 1'b1;
                     `else
                     illegal_instr_o = 1'b1; // Not supported
-                    `endif
+                    `endif // EN_EXCEPT
 
                 end
                 else if(rd_sel_o == 5'b00000 && func3 == 3'b000 && rs1_sel_o == 5'b00000 && rs2_sel_o == 5'b00101 && func7 == 7'b0001000) /* WFI */ begin
                     instr_scope = "WFI";
                     illegal_instr_o = 1'b1; // Not supported
                 end
                 else begin
-                    `ifdef RV_ZICSR
+                    `ifdef EN_RVZICSR
                         /* CSR Instructions */
                         case(func3)
                             3'b001: instr_scope = "CSRRW";
@@ -549,7 +549,7 @@ module Decode
                         imm_format = `RV_IMM_TYPE_I;
                     `else
                         illegal_instr_o = 1'b1;
-                    `endif // RV_ZICSR
+                    `endif // EN_RVZICSR
                 end
             end
 
@@ -566,9 +566,9 @@ module Decode
                 mem_we_o = 1'b0;
                 imm_format = 0;
 
-                `ifdef RV_ZICSR
+                `ifdef EN_RVZICSR
                 csru_we_o = 0;
-                `endif
+                `endif // EN_RVZICSR
 
                 `ifdef EN_EXCEPT
                 trap_ret_o = 0;

diff --git a/rtl/soc/hydrogensoc/HydrogenSoC.v b/rtl/soc/hydrogensoc/HydrogenSoC.v
@@ -451,8 +451,8 @@ module HydrogenSoC(
         .int_o      (timer_int_o)
     );
 
-    `ifndef RV_EXCEPT
+    `ifndef EN_EXCEPT
     `UNUSED_VAR(timer_int_o)
-    `endif // RV_EXCEPT
+    `endif // EN_EXCEPT
 
 endmodule
diff --git a/rtl/soc/hydrogensoc/HydrogenSoC_Config.vh b/rtl/soc/hydrogensoc/HydrogenSoC_Config.vh
@@ -15,50 +15,6 @@
 `define SOC_RESET_ADDRESS   32'h0001_0000
 `endif
 
-/*
-    If defined, enables the RVE extenstion which disables the upper 16 registers 
-    in the register file.
-*/
-`ifdef ENABLE_RISCV_EMBEDDED
-`define RV_E
-`endif
-
-/*
-    If defined, enables the RISC-V Zicsr extension which adds support for CSR 
-    registers. It adds a CSR Unit to the Core which implements CSR registers 
-    like CYCLEL/H.
-*/
-`ifdef ENABLE_RISCV_ZICSR
-`define RV_ZICSR
-`endif
-
-/*
-    If defined, enables the RISC-V Compressed extension which adds support for 16-bit 
-    compressed instructions. It adds a decoder which decodes the 16 bit instructions 
-    to 32 bit equivalents and a aligner to word-align Instruction fetches.
-*/
-`ifdef ENABLE_RISCV_COMPRESSED
-`define RV_C
-`endif
-
-/*
-    If defined enables exceptions and interrupts
-*/
-`ifdef ENABLE_RISCV_EXCEPTIONS
-`define RV_ZICSR
-`define EN_EXCEPT
-`endif
-
-// Define number of GPIO Pins to implement
-`ifndef NGPIO
-`define NGPIO 32
-`endif
-
-// Define number of CHIP select lines for SPI
-`ifndef NSPI_CS
-`define NSPI_CS 1
-`endif
-
 
 ////////////////////////////// SoC Memory Map //////////////////////////////
 // Macros used by Wishbone interconnect