Merge pull request #473 from sifive/scrub_mem

Update BSPs for ecc memory scrub. Bump submodules.
sifive · Apr 30, 2020 · 64d9a5c · 64d9a5c
2 parents c57e97f + 2696892
commit 64d9a5c
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Showing 30 changed files with 72 additions and 25 deletions.
diff --git a/bsp/freedom-e310-arty/metal-inline.h b/bsp/freedom-e310-arty/metal-inline.h
@@ -192,6 +192,7 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
 /* From cpu@0 */
 struct __metal_driver_cpu __metal_dt_cpu_0 = {
     .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+    .hpm_count = 0,
 };
 
 /* From interrupt_controller */

diff --git a/bsp/qemu-sifive-e31/metal-inline.h b/bsp/qemu-sifive-e31/metal-inline.h
@@ -227,6 +227,7 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
 /* From cpu@0 */
 struct __metal_driver_cpu __metal_dt_cpu_0 = {
     .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+    .hpm_count = 0,
 };
 
 /* From interrupt_controller */

diff --git a/bsp/qemu-sifive-s51/metal-inline.h b/bsp/qemu-sifive-s51/metal-inline.h
@@ -227,6 +227,7 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
 /* From cpu@0 */
 struct __metal_driver_cpu __metal_dt_cpu_0 = {
     .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+    .hpm_count = 0,
 };
 
 /* From interrupt_controller */

diff --git a/bsp/qemu-sifive-u54/metal-inline.h b/bsp/qemu-sifive-u54/metal-inline.h
@@ -140,6 +140,7 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
 /* From cpu@0 */
 struct __metal_driver_cpu __metal_dt_cpu_0 = {
     .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+    .hpm_count = 0,
 };
 
 /* From interrupt_controller */

diff --git a/bsp/qemu-sifive-u54/metal.default.lds b/bsp/qemu-sifive-u54/metal.default.lds
@@ -73,8 +73,10 @@ SECTIONS
     PROVIDE(__metal_eccscrub_bit = 0);
 
     /* The RAM memories map for ECC scrubbing */
+    /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */
+    /* User is recommended to enable the full size for manual RTL simulation run! */
     PROVIDE( metal_memory_0_memory_start = 0x80000000 );
-    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x80000000 );
+    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 );
 
     /* ROM SECTION
      *

diff --git a/bsp/qemu-sifive-u54/metal.freertos.lds b/bsp/qemu-sifive-u54/metal.freertos.lds
@@ -76,8 +76,10 @@ SECTIONS
     PROVIDE(__metal_eccscrub_bit = 0);
 
     /* The RAM memories map for ECC scrubbing */
+    /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */
+    /* User is recommended to enable the full size for manual RTL simulation run! */
     PROVIDE( metal_memory_0_memory_start = 0x80000000 );
-    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x80000000 );
+    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 );
 
     /* ROM SECTION
      *

diff --git a/bsp/qemu-sifive-u54/metal.ramrodata.lds b/bsp/qemu-sifive-u54/metal.ramrodata.lds
@@ -77,8 +77,10 @@ SECTIONS
     PROVIDE(__metal_eccscrub_bit = 0);
 
     /* The RAM memories map for ECC scrubbing */
+    /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */
+    /* User is recommended to enable the full size for manual RTL simulation run! */
     PROVIDE( metal_memory_0_memory_start = 0x80000000 );
-    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x80000000 );
+    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 );
 
     /* ROM SECTION
      *

diff --git a/bsp/qemu-sifive-u54/metal.scratchpad.lds b/bsp/qemu-sifive-u54/metal.scratchpad.lds
@@ -74,8 +74,10 @@ SECTIONS
     PROVIDE(__metal_eccscrub_bit = 0);
 
     /* The RAM memories map for ECC scrubbing */
+    /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */
+    /* User is recommended to enable the full size for manual RTL simulation run! */
     PROVIDE( metal_memory_0_memory_start = 0x80000000 );
-    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x80000000 );
+    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 );
 
     /* ROM SECTION
      *

diff --git a/bsp/qemu-sifive-u54mc/metal-inline.h b/bsp/qemu-sifive-u54mc/metal-inline.h
@@ -148,21 +148,25 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
 /* From cpu@0 */
 struct __metal_driver_cpu __metal_dt_cpu_0 = {
     .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+    .hpm_count = 0,
 };
 
 /* From cpu@1 */
 struct __metal_driver_cpu __metal_dt_cpu_1 = {
     .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+    .hpm_count = 0,
 };
 
 /* From cpu@2 */
 struct __metal_driver_cpu __metal_dt_cpu_2 = {
     .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+    .hpm_count = 0,
 };
 
 /* From cpu@3 */
 struct __metal_driver_cpu __metal_dt_cpu_3 = {
     .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+    .hpm_count = 0,
 };
 
 /* From interrupt_controller */

diff --git a/bsp/qemu-sifive-u54mc/metal.default.lds b/bsp/qemu-sifive-u54mc/metal.default.lds
@@ -73,8 +73,10 @@ SECTIONS
     PROVIDE(__metal_eccscrub_bit = 0);
 
     /* The RAM memories map for ECC scrubbing */
+    /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */
+    /* User is recommended to enable the full size for manual RTL simulation run! */
     PROVIDE( metal_memory_0_memory_start = 0x80000000 );
-    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x80000000 );
+    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 );
 
     /* ROM SECTION
      *

diff --git a/bsp/qemu-sifive-u54mc/metal.freertos.lds b/bsp/qemu-sifive-u54mc/metal.freertos.lds
@@ -76,8 +76,10 @@ SECTIONS
     PROVIDE(__metal_eccscrub_bit = 0);
 
     /* The RAM memories map for ECC scrubbing */
+    /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */
+    /* User is recommended to enable the full size for manual RTL simulation run! */
     PROVIDE( metal_memory_0_memory_start = 0x80000000 );
-    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x80000000 );
+    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 );
 
     /* ROM SECTION
      *

diff --git a/bsp/qemu-sifive-u54mc/metal.ramrodata.lds b/bsp/qemu-sifive-u54mc/metal.ramrodata.lds
@@ -77,8 +77,10 @@ SECTIONS
     PROVIDE(__metal_eccscrub_bit = 0);
 
     /* The RAM memories map for ECC scrubbing */
+    /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */
+    /* User is recommended to enable the full size for manual RTL simulation run! */
     PROVIDE( metal_memory_0_memory_start = 0x80000000 );
-    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x80000000 );
+    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 );
 
     /* ROM SECTION
      *

diff --git a/bsp/qemu-sifive-u54mc/metal.scratchpad.lds b/bsp/qemu-sifive-u54mc/metal.scratchpad.lds
@@ -74,8 +74,10 @@ SECTIONS
     PROVIDE(__metal_eccscrub_bit = 0);
 
     /* The RAM memories map for ECC scrubbing */
+    /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */
+    /* User is recommended to enable the full size for manual RTL simulation run! */
     PROVIDE( metal_memory_0_memory_start = 0x80000000 );
-    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x80000000 );
+    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 );
 
     /* ROM SECTION
      *

diff --git a/bsp/sifive-hifive-unleashed/metal-inline.h b/bsp/sifive-hifive-unleashed/metal-inline.h
@@ -284,26 +284,31 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
 /* From cpu@0 */
 struct __metal_driver_cpu __metal_dt_cpu_0 = {
     .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+    .hpm_count = 0,
 };
 
 /* From cpu@1 */
 struct __metal_driver_cpu __metal_dt_cpu_1 = {
     .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+    .hpm_count = 0,
 };
 
 /* From cpu@2 */
 struct __metal_driver_cpu __metal_dt_cpu_2 = {
     .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+    .hpm_count = 0,
 };
 
 /* From cpu@3 */
 struct __metal_driver_cpu __metal_dt_cpu_3 = {
     .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+    .hpm_count = 0,
 };
 
 /* From cpu@4 */
 struct __metal_driver_cpu __metal_dt_cpu_4 = {
     .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+    .hpm_count = 0,
 };
 
 /* From interrupt_controller */

diff --git a/bsp/sifive-hifive-unleashed/metal.default.lds b/bsp/sifive-hifive-unleashed/metal.default.lds
@@ -81,8 +81,10 @@ SECTIONS
     PROVIDE( metal_itim_0_memory_end = 0x1800000 + 0x4000 );
     PROVIDE( metal_itim_1_memory_start = 0x1808000 );
     PROVIDE( metal_itim_1_memory_end = 0x1808000 + 0x20000 );
+    /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */
+    /* User is recommended to enable the full size for manual RTL simulation run! */
     PROVIDE( metal_memory_0_memory_start = 0x80000000 );
-    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x1f80000000 );
+    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 );
 
     /* ROM SECTION
      *

diff --git a/bsp/sifive-hifive-unleashed/metal.freertos.lds b/bsp/sifive-hifive-unleashed/metal.freertos.lds
@@ -84,8 +84,10 @@ SECTIONS
     PROVIDE( metal_itim_0_memory_end = 0x1800000 + 0x4000 );
     PROVIDE( metal_itim_1_memory_start = 0x1808000 );
     PROVIDE( metal_itim_1_memory_end = 0x1808000 + 0x20000 );
+    /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */
+    /* User is recommended to enable the full size for manual RTL simulation run! */
     PROVIDE( metal_memory_0_memory_start = 0x80000000 );
-    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x1f80000000 );
+    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 );
 
     /* ROM SECTION
      *

diff --git a/bsp/sifive-hifive-unleashed/metal.ramrodata.lds b/bsp/sifive-hifive-unleashed/metal.ramrodata.lds
@@ -85,8 +85,10 @@ SECTIONS
     PROVIDE( metal_itim_0_memory_end = 0x1800000 + 0x4000 );
     PROVIDE( metal_itim_1_memory_start = 0x1808000 );
     PROVIDE( metal_itim_1_memory_end = 0x1808000 + 0x20000 );
+    /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */
+    /* User is recommended to enable the full size for manual RTL simulation run! */
     PROVIDE( metal_memory_0_memory_start = 0x80000000 );
-    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x1f80000000 );
+    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 );
 
     /* ROM SECTION
      *

diff --git a/bsp/sifive-hifive-unleashed/metal.scratchpad.lds b/bsp/sifive-hifive-unleashed/metal.scratchpad.lds
@@ -82,8 +82,10 @@ SECTIONS
     PROVIDE( metal_itim_0_memory_end = 0x1800000 + 0x4000 );
     PROVIDE( metal_itim_1_memory_start = 0x1808000 );
     PROVIDE( metal_itim_1_memory_end = 0x1808000 + 0x20000 );
+    /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */
+    /* User is recommended to enable the full size for manual RTL simulation run! */
     PROVIDE( metal_memory_0_memory_start = 0x80000000 );
-    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x1f80000000 );
+    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 );
 
     /* ROM SECTION
      *

diff --git a/bsp/sifive-hifive1-revb/metal-inline.h b/bsp/sifive-hifive1-revb/metal-inline.h
@@ -265,6 +265,7 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
 /* From cpu@0 */
 struct __metal_driver_cpu __metal_dt_cpu_0 = {
     .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+    .hpm_count = 0,
 };
 
 /* From interrupt_controller */

diff --git a/bsp/sifive-hifive1/metal-inline.h b/bsp/sifive-hifive1/metal-inline.h
@@ -225,6 +225,7 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
 /* From cpu@0 */
 struct __metal_driver_cpu __metal_dt_cpu_0 = {
     .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+    .hpm_count = 0,
 };
 
 /* From interrupt_controller */

diff --git a/bsp/spike/metal-inline.h b/bsp/spike/metal-inline.h
@@ -124,6 +124,7 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
 /* From cpu@0 */
 struct __metal_driver_cpu __metal_dt_cpu_0 = {
     .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+    .hpm_count = 0,
 };
 
 /* From interrupt_controller */

diff --git a/bsp/spike/metal.default.lds b/bsp/spike/metal.default.lds
@@ -73,8 +73,10 @@ SECTIONS
     PROVIDE(__metal_eccscrub_bit = 0);
 
     /* The RAM memories map for ECC scrubbing */
+    /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */
+    /* User is recommended to enable the full size for manual RTL simulation run! */
     PROVIDE( metal_memory_0_memory_start = 0x80000000 );
-    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x80000000 );
+    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 );
 
     /* ROM SECTION
      *

diff --git a/bsp/spike/metal.freertos.lds b/bsp/spike/metal.freertos.lds
@@ -76,8 +76,10 @@ SECTIONS
     PROVIDE(__metal_eccscrub_bit = 0);
 
     /* The RAM memories map for ECC scrubbing */
+    /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */
+    /* User is recommended to enable the full size for manual RTL simulation run! */
     PROVIDE( metal_memory_0_memory_start = 0x80000000 );
-    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x80000000 );
+    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 );
 
     /* ROM SECTION
      *

diff --git a/bsp/spike/metal.ramrodata.lds b/bsp/spike/metal.ramrodata.lds
@@ -77,8 +77,10 @@ SECTIONS
     PROVIDE(__metal_eccscrub_bit = 0);
 
     /* The RAM memories map for ECC scrubbing */
+    /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */
+    /* User is recommended to enable the full size for manual RTL simulation run! */
     PROVIDE( metal_memory_0_memory_start = 0x80000000 );
-    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x80000000 );
+    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 );
 
     /* ROM SECTION
      *

diff --git a/bsp/spike/metal.scratchpad.lds b/bsp/spike/metal.scratchpad.lds
@@ -74,8 +74,10 @@ SECTIONS
     PROVIDE(__metal_eccscrub_bit = 0);
 
     /* The RAM memories map for ECC scrubbing */
+    /* Default memory to zero-scrub for at most 64KB, for limiting RTL simulation run time. */
+    /* User is recommended to enable the full size for manual RTL simulation run! */
     PROVIDE( metal_memory_0_memory_start = 0x80000000 );
-    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x80000000 );
+    PROVIDE( metal_memory_0_memory_end = 0x80000000 + 0x10000 );
 
     /* ROM SECTION
      *

diff --git a/debug.mk b/debug.mk
@@ -9,6 +9,5 @@ RISCV_CXXFLAGS += -O0
 
 # Enable debug
 RISCV_ASFLAGS += -g
-RISCV_CFLAGS += -g
-RISCV_CXXFLAGS += -g
-
+RISCV_CFLAGS += -g -mno-relax
+RISCV_CXXFLAGS += -g -mno-relax
diff --git a/freedom-devicetree-tools b/freedom-devicetree-tools
diff --git a/freedom-metal b/freedom-metal
diff --git a/scripts/ldscript-generator b/scripts/ldscript-generator
diff --git a/wit-manifest.json b/wit-manifest.json
@@ -1,11 +1,11 @@
 [
     {
-        "commit": "2a460ff2428afaf2e8dd2b3d8322307382638289",
+        "commit": "becd685e7fbbe99f97b3c8379625b7d8b69b97c8",
         "name": "freedom-devicetree-tools",
         "source": "[email protected]:sifive/freedom-devicetree-tools.git"
     },
     {
-        "commit": "69d2038f6f09e5818164d076825b10fff6fe7f7f",
+        "commit": "2e39b117f3dae7ab5e71aa0d184a0854e9b22295",
         "name": "freedom-metal",
         "source": "[email protected]:sifive/freedom-metal.git"
     },
@@ -20,7 +20,7 @@
         "source": "[email protected]:sifive/devicetree-overlay-generator.git"
     },
     {
-        "commit": "6f0944f030425fef4eb54176780eab84b1670e0d",
+        "commit": "c13f43e3756d81f7c5e3103ebefd968a9af2117d",
         "name": "ldscript-generator",
         "source": "[email protected]:sifive/ldscript-generator.git"
     },
+1 −0		Makefile.am
+19 −15		Makefile.in
+25 −25		aclocal.m4
+0 −1		src/entry.S
+117 −0		src/scrub.S