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minor cleanup of asic soc design folders
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-epochs0-gf12: fix defconfig
-esp_asic_generic: uncomment vsim.tcl to fix JTAG simulation
-esp_asic_generrric: fix whitespace in fpga_proxy_top.vhd
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jzuckerman committed Feb 3, 2023
1 parent db03395 commit d0e52ff
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Showing 3 changed files with 35 additions and 34 deletions.
15 changes: 8 additions & 7 deletions socs/epochs0-gf12/esp_epochs0_defconfig
Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@ CONFIG_ACC_CACHES = 512 4
CONFIG_SLM_KBYTES = 256
CONFIG_JTAG_EN = y
CONFIG_ETH_EN = y
#CONFIG_IOLINK_EN is not set
#CONFIG_SVGA_EN is not set
CONFIG_DSU_IP = C0A80113
CONFIG_DSU_ETH = A6A7A0F81440
Expand All @@ -23,21 +24,21 @@ CONFIG_DSU_ETH = A6A7A0F81440
#CONFIG_MON_LLC is not set
#CONFIG_MON_DVFS is not set
TILE_0_0 = 0 misc IO 0 0 0
TILE_0_1 = 1 acc NV_NVDLA 0 0 0 0 0 nvidia
TILE_0_2 = 2 acc NV_NVDLA 0 0 0 0 0 nvidia
TILE_0_3 = 3 acc NV_NVDLA 0 0 0 0 0 nvidia
TILE_1_0 = 4 acc FFT_STRATUS 0 0 0 basic_fx32_dma64 0 0 sld
TILE_0_1 = 1 acc NV_NVDLA 0 0 0 0 nvidia
TILE_0_2 = 2 acc NV_NVDLA 0 0 0 0 nvidia
TILE_0_3 = 3 acc NV_NVDLA 0 0 0 0 nvidia
TILE_1_0 = 4 acc FFT_STRATUS 0 0 0 basic_fx32_dma64 0 sld
TILE_1_1 = 5 cpu cpu 0 0 0 0
TILE_1_2 = 6 cpu cpu 0 0 0 0
TILE_1_3 = 7 mem mem 0 0 0
TILE_2_0 = 8 acc FFT_STRATUS 0 0 0 basic_fx32_dma64 0 0 sld
TILE_2_0 = 8 acc FFT_STRATUS 0 0 0 basic_fx32_dma64 0 sld
TILE_2_1 = 9 cpu cpu 0 0 0 0
TILE_2_2 = 10 cpu cpu 0 0 0 0
TILE_2_3 = 11 mem mem 0 0 0
TILE_3_0 = 12 acc FFT_STRATUS 0 0 0 basic_fx32_dma64 0 0 sld
TILE_3_0 = 12 acc FFT_STRATUS 0 0 0 basic_fx32_dma64 0 sld
TILE_3_1 = 13 mem mem 0 0 0
TILE_3_2 = 14 mem mem 0 0 0
TILE_3_3 = 15 acc VITDODEC_STRATUS 0 0 0 basic_dma64 0 0 sld
TILE_3_3 = 15 acc VITDODEC_STRATUS 0 0 0 basic_dma64 0 sld
#CONFIG_HAS_DVFS is not set
CONFIG_VF_POINTS = 4
POWER_0_0 = IO 0 0 0 0 0 0 0 0 0 0 0 0
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44 changes: 22 additions & 22 deletions socs/esp_asic_generic/fpga_proxy_top.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -1233,27 +1233,27 @@ begin -- architecture rtl
end generate iolink_sim_gen;

iolink_no_sim_gen: if SIMULATION = false generate
ahbslv2iolink_i : ahbslv2iolink
generic map (
hindex => 2,
hconfig => iolink_hconfig,
io_bitwidth => CFG_IOLINK_BITS,
word_bitwidth => 32,
little_end => 0 )
port map (
clk => main_clk,
rstn => rstn,
io_clk_in => iolink_clk_in_int,
io_clk_out => iolink_clk_out_int,
io_valid_in => iolink_valid_in_int,
io_valid_out => iolink_valid_out_int,
io_credit_in => iolink_credit_in_int,
io_credit_out => iolink_credit_out_int,
io_data_oen => iolink_data_oen,
io_data_in => iolink_data_in_int,
io_data_out => iolink_data_out_int,
ahbsi => ahbsi,
ahbso => ahbso_iolink);
end generate iolink_no_sim_gen;
ahbslv2iolink_i : ahbslv2iolink
generic map (
hindex => 2,
hconfig => iolink_hconfig,
io_bitwidth => CFG_IOLINK_BITS,
word_bitwidth => 32,
little_end => 0 )
port map (
clk => main_clk,
rstn => rstn,
io_clk_in => iolink_clk_in_int,
io_clk_out => iolink_clk_out_int,
io_valid_in => iolink_valid_in_int,
io_valid_out => iolink_valid_out_int,
io_credit_in => iolink_credit_in_int,
io_credit_out => iolink_credit_out_int,
io_data_oen => iolink_data_oen,
io_data_in => iolink_data_in_int,
io_data_out => iolink_data_out_int,
ahbsi => ahbsi,
ahbso => ahbso_iolink);
end generate iolink_no_sim_gen;

end architecture rtl;
10 changes: 5 additions & 5 deletions socs/esp_asic_generic/vsim.tcl
Original file line number Diff line number Diff line change
@@ -1,12 +1,12 @@
#echo "Restarting simulation with SDF annotation for GF12 DCO and delay line"
#set sdf ""
#set TECHLIB $::env(TECHLIB)
#set ESP_ROOT $::env(ESP_ROOT)
#set VSIMOPT $::env(VSIMOPT)
set sdf ""
set TECHLIB $::env(TECHLIB)
set ESP_ROOT $::env(ESP_ROOT)
set VSIMOPT $::env(VSIMOPT)
#foreach inst [find instances -nodu -bydu DCO_GF12_C14] {
# append sdf "-sdfmax "
# append sdf [string map {( [} [string map {) ]} $inst]]
# append sdf "=${ESP_ROOT}/rtl/techmap/${TECHLIB}/wrappers/DCO_tt.sdf "
#}
#append sdf "-suppress 3438"
#eval vsim $sdf $VSIMOPT
eval vsim $sdf $VSIMOPT

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