Cg integrate ip1 #2

gingu · 2024-07-25T18:03:49Z

To @bparpillon @badeaa3 Let me know when is a good time for this merge. Because, before merging this branch 'cg_integrate_ip1' (which we verified it works on hardware chain of 3 PCBs,) I would like you to check/confirm that this pull request will preserve (include into main branch) all your updates in Python routines and the other two (?) submodules.
The tab "Files changed" above shows the merge should be OK, but I want yo also to confirm. It shows >600 files changed, but now the .gitignore is updated with the following lines:

vivado/cms_pix_28_test_firmware.cache/*
vivado/cms_pix_28_test_firmware.gen/*
vivado/cms_pix_28_test_firmware.runs/*

so all these folders, while already present in main, will not be updated

…build

…S up to TEST 3

…config_clk

…ware.runs/

…ware.gen/

…che/ip/* and vivado/cms_pix_28_test_firmware.cache/wt/*

…d fw_ip2.sv

…-caribou-common-blocks

…fw_ip1/2/3/4.sv

…w_to_dut.sv

…nabled, regardless of fw_dev_id_enable being HIGH or LOW

…fined BXCLK/ANA 40MHz with 5ns delay

… 2*768=1536 bxclk cycles

badeaa3 · 2024-07-30T12:24:48Z

Hi @gingu many many thanks (and hello from Krakow, Poland). I was talking with @bparpillon about testing things. If I understood right @bparpillon verified part of it and we have more work to do then we can merge it. Let's get more comments from him

Cristinel Gingu added 28 commits June 28, 2024 18:08

CG new src/configclk_generator.sv; new .dvt/cms_pix_28_test_firmware.…

360ed01

…build

CG cosmetic src/fw_ip2.sv src/fw_ipx_wrap.sv

31fe664

CG cosmetic vrf/fw_ipx_wrap_tb.sv

44a7b8a

CG updated code src/fw_ip1.sv with test1 following src/fw_ip2.sv pattern

64732ca

CG new module src/ip1_test1.sv following src/ip2_test1.sv pattern

9c1045e

CG new vrf/fw_ipx_wrap_tb_ip1.sv following vrf/fw_ipx_wrap_tb.sv; PAS…

c468387

…S up to TEST 3

CG new waveform file vrf/fw_ipx_wrap_tb_ip1.svwf

db7485a

CG update .gitignore

edf3548

CG add test3 and test4 debug test for oscilloscope tracing fast/slow_…

87f4b89

…config_clk

CG Vivado folder after git rm -r --cached vivado/cms_pix_28_test_firm…

5231373

…ware.runs/

CG Vivado folder after git rm -r --cached vivado/cms_pix_28_test_firm…

0aeb283

…ware.gen/

CG Vivado commit with .gitignore update

76d5cca

CG Vivado after git rm -r --cached vivado/cms_pix_28_test_firmware.ca…

2f0f4e7

…che/ip/* and vivado/cms_pix_28_test_firmware.cache/wt/*

Merge remote-tracking branch 'origin/main' into cg_integrate_ip1

dd940e3

CG add Test5 and Test6

fe9052d

CG factorize new module src/com_testx_decoder.sv used in fw_ip1.sv an…

0002893

…d fw_ip2.sv

CG update Vivado; only 6 files

e62df23

CG axilite now pointing to submodule instead off directily to spacely…

a1ddb8b

…-caribou-common-blocks

CG update constraint file cms_pix_28_test_firmware.xdc

ca5c3c5

CG update Vivado with new constraint file cms_pix_28_test_firmware.xdc

3546f79

CG Clean header file Description and Author

6f2e571

CG update Vivado after Clean header file Description and Author

da3254f

CG Update default values: fw_reset_not=1'b1; fw_config_load=1'b1; in …

9358af8

…fw_ip1/2/3/4.sv

CG Make outputs bxclk and bxclk_ana driven only by fw_ip2.sv in com_t…

6c9ff39

…w_to_dut.sv

CG Update bxclks_generators_inst to make bxclk and bxclk_ana always e…

5024472

…nabled, regardless of fw_dev_id_enable being HIGH or LOW

CG update fw_ipx_wrap_tb_ip1.sv with Test 21: IP2 related - set prede…

16e9933

…fined BXCLK/ANA 40MHz with 5ns delay

CG Change tests length from 768 bxclk cycles to 2*768=1536 bxclk cycles

bb49182

CG update Vivado after changing tests length from 768 bxclk cycles to…

e8c106f

… 2*768=1536 bxclk cycles

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Cg integrate ip1 #2

Cg integrate ip1 #2

gingu commented Jul 25, 2024 •

edited

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badeaa3 commented Jul 30, 2024

Cg integrate ip1 #2

Are you sure you want to change the base?

Cg integrate ip1 #2

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gingu commented Jul 25, 2024 • edited Loading

badeaa3 commented Jul 30, 2024

gingu commented Jul 25, 2024 •

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