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Corrected register #5

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3 changes: 3 additions & 0 deletions .idea/.gitignore

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11 changes: 11 additions & 0 deletions .idea/SparkFun_Clock_5P49V60_Arduino_Library.iml

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6 changes: 6 additions & 0 deletions .idea/inspectionProfiles/profiles_settings.xml

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4 changes: 4 additions & 0 deletions .idea/misc.xml

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8 changes: 8 additions & 0 deletions .idea/modules.xml

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6 changes: 6 additions & 0 deletions .idea/vcs.xml

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Original file line number Diff line number Diff line change
Expand Up @@ -62,7 +62,20 @@ void setup(){
// Fist, Setting the internal oscillator to a known value that makes for easy
// division: 1600MHz. 1600MHz/16MHz = 100
Serial.println("Setting Integer Divider.");
clockGen.setPllFeedbackIntDiv(100);
//clockGen.setPllFeedbackIntDiv(200);
// Fist, Setting the internal oscillator to a known value.
Serial.println("Setting Internal Clock Frequency to 3200MHz.");
clockGen.setVcoFrequency(3200.0); // Give float value in MHz

// Clock One----------------------------------------------------
// Use internal phase lock loop for clock output calculation.

Serial.println("Setting Output Mode for Clock One to LVDS.");
// There are many OUTPUT modes available for each clock - this example uses
// LVPECL (Low voltage Positive Emitter Coupled Logic) mode.

Serial.println("Setting Clock One Frequency to 125MHz.");
clockGen.setClockOneFreq(125.0); // Give float value in MHz, 8.0 = 8000000Hz or 8MHz
Serial.print("Integer Divider set to: ");
uint16_t fbVal = clockGen.readPllFeedBackIntDiv();
Serial.println(fbVal);
Expand All @@ -73,8 +86,8 @@ void setup(){
// Fractional portion = .36 -> Need to convert to a HEX value
// 2^24 * .36 = 6039796.76
// Round the value to closest integer = 6039797
clockGen.setIntDivOutOne(36);
clockGen.setFractDivFodOne(6039797);
//clockGen.setIntDivOutOne(12);
//clockGen.setFractDivFodOne(13421773);
Serial.print("FOD One Integer Divider: ");
Serial.println(clockGen.readIntDivOutOne());
Serial.print("FOD One Fractional Divider: ");
Expand All @@ -83,7 +96,7 @@ void setup(){
// There are many OUTPUT modes available for each clock - this example uses
// LVPECL (Low voltage Positive Emitter Coupled Logic) mode and terminates
// the clock with a 100Ohm resistance to GND.
clockGen.clockOneConfigMode(LVPECL_MODE);
clockGen.clockOneConfigMode(LVDS_MODE);
clockGen.clockOneControl(ENABLE);
// --------------------------------------------------------------

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