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CHB:ARM: add sizes to operands
1 parent f303317 commit 120932a

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3 files changed

+57
-43
lines changed

3 files changed

+57
-43
lines changed

‎CodeHawk/CHB/bchlib/bCHTypeConstraintStore.ml‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -692,8 +692,8 @@ object (self)
692692
Some (t_ptrto (type_constant_to_btype c))
693693
| [Store; OffsetAccess _] ->
694694
Some (t_ptrto (type_constant_to_btype c))
695-
| [OffsetAccessA (_size, _)] ->
696-
Some (t_array (type_constant_to_btype c) 1)
695+
| [OffsetAccessA (size, _)] ->
696+
Some (t_array (type_constant_to_btype c) size)
697697
| _ -> None in
698698
match optty with
699699
| Some ty -> result#add (bcd#index_typ ty)

‎CodeHawk/CHB/bchlibarm32/bCHDisassembleARMInstruction.ml‎

Lines changed: 24 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -215,7 +215,8 @@ let parse_data_proc_reg_load_stores
215215
let rn = arm_register_op rnreg (if iswback then RW else RD) in
216216
let rm = arm_register_op rmreg RD in
217217
let offset = arm_index_offset rmreg in
218-
let mem = mk_arm_offset_address_op rnreg offset ~isadd ~isindex ~iswback WR in
218+
let mem =
219+
mk_arm_offset_address_op rnreg offset ~size:2 ~isadd ~isindex ~iswback WR in
219220
(* STRH{<c>} <Rt>, [<Rn>, +/-<Rm>]{!} Pre-x : (index,wback) = (T,T/F)
220221
* STRH{<c>} <Rt>, [<Rn>], +/-<Rm> Post-x: (index,wback) = (F,T) *)
221222
StoreRegisterHalfword (c, rt, rn, rm, mem, false)
@@ -264,7 +265,8 @@ let parse_data_proc_reg_load_stores
264265
let rn = arm_register_op rnreg (if iswback then RW else RD) in
265266
let rm = arm_register_op rmreg RD in
266267
let offset = arm_index_offset rmreg in
267-
let mem = mk_arm_offset_address_op rnreg offset ~isadd ~isindex ~iswback RD in
268+
let mem =
269+
mk_arm_offset_address_op rnreg offset ~size:2 ~isadd ~isindex ~iswback RD in
268270
(* LDRH<c> <Rt>, [<Rn>, +/-<Rm>]{!} Pre-x : (index,wback) = (T,T/F)
269271
* LDRH<c> <Rt>, [<Rn>], +/-<Rm> Post-x: (index,wback) = (F,T) *)
270272
LoadRegisterHalfword (c, rt, rn, rm, mem, false)
@@ -277,7 +279,8 @@ let parse_data_proc_reg_load_stores
277279
let rn = arm_register_op rnreg (if iswback then RW else RD) in
278280
let rm = arm_register_op rmreg RD in
279281
let offset = arm_index_offset rmreg in
280-
let mem = mk_arm_offset_address_op rnreg offset ~isadd ~isindex ~iswback RD in
282+
let mem =
283+
mk_arm_offset_address_op rnreg offset ~size:1 ~isadd ~isindex ~iswback RD in
281284
(* LDRSB<c> <Rt>, [<Rn>,+/-<Rm>]{!}
282285
* LDRSB<c> <Rt>, [<Rn>],+/-<Rm> *)
283286
LoadRegisterSignedByte (c, rt, rn, rm, mem, false)
@@ -290,7 +293,8 @@ let parse_data_proc_reg_load_stores
290293
let rn = arm_register_op rnreg (if iswback then RW else RD) in
291294
let rm = arm_register_op rmreg RD in
292295
let offset = arm_index_offset rmreg in
293-
let mem = mk_arm_offset_address_op rnreg offset ~isadd ~isindex ~iswback RD in
296+
let mem =
297+
mk_arm_offset_address_op rnreg offset ~size:2 ~isadd ~isindex ~iswback RD in
294298
(* LDRSH<c> <Rt>, [<Rn>,+/-<Rm>]{!} *)
295299
(* LDRSH<c> <Rt>, [<Rn>],+/-<rm> *)
296300
LoadRegisterSignedHalfword (c, rt, rn, rm, mem, false)
@@ -308,7 +312,8 @@ let parse_data_proc_reg_load_stores
308312
(signed_immediate_from_int imm32) in
309313
let imm = arm_immediate_op imm in
310314
let offset = ARMImmOffset imm32 in
311-
let mem = mk_arm_offset_address_op rnreg offset ~isadd ~isindex ~iswback WR in
315+
let mem =
316+
mk_arm_offset_address_op rnreg offset ~size:2 ~isadd ~isindex ~iswback WR in
312317
(* STRH<c> <Rt>, [<Rn>{, #+/-<imm8>}] Offset: (index,wback) = (T,F)
313318
* STRH<c> <Rt>, [<Rn>, #+/-<imm>]! Pre-x : (index,wback) = (T,T)
314319
* STRH<c> <Rt>, [<Rn>], #+/-<imm> Post-x: (index,wback) = (F,T) *)
@@ -385,7 +390,8 @@ let parse_data_proc_reg_load_stores
385390
(signed_immediate_from_int imm32) in
386391
let imm = arm_immediate_op imm in
387392
let offset = ARMImmOffset imm32 in
388-
let mem = mk_arm_offset_address_op rnreg offset ~isadd ~isindex ~iswback RD in
393+
let mem =
394+
mk_arm_offset_address_op rnreg offset ~size:2 ~isadd ~isindex ~iswback RD in
389395
(* LDRH<c> <Rt>, [<Rn>{, #+/-<imm>}] Offset: (index,wback) = (T,F)
390396
* LDRH<c> <Rt>, [<Rn>, #+/-<imm>]! Pre-x : (index,wback) = (T,T)
391397
* LDRH<c> <Rt>, [<Rn>], #+/-<imm> Post-x: (index,wback) = (F,T) *)
@@ -404,7 +410,8 @@ let parse_data_proc_reg_load_stores
404410
(signed_immediate_from_int imm32) in
405411
let imm = arm_immediate_op imm in
406412
let offset = ARMImmOffset imm32 in
407-
let mem = mk_arm_offset_address_op rnreg offset ~isadd ~isindex ~iswback RD in
413+
let mem =
414+
mk_arm_offset_address_op rnreg offset ~size:1 ~isadd ~isindex ~iswback RD in
408415
(* LDRSB<c> <Rt>, [<Rn>{, #+/-<imm8>}]
409416
* LDRSB<c> <Rt>, [<Rn>], #+/-<imm8>
410417
* LDRSB<c> <Rt>, [<Rn>, #+/-<imm8>]! *)
@@ -423,7 +430,8 @@ let parse_data_proc_reg_load_stores
423430
(signed_immediate_from_int imm32) in
424431
let imm = arm_immediate_op imm in
425432
let offset = ARMImmOffset imm32 in
426-
let mem = mk_arm_offset_address_op rnreg offset ~isadd ~isindex ~iswback RD in
433+
let mem =
434+
mk_arm_offset_address_op rnreg offset ~size:2 ~isadd ~isindex ~iswback RD in
427435
(* LDRSH<c> <Rt>, [<Rn>{, #+/-<imm8>}]
428436
* LDRSH<c> <Rt>, [<Rn>], #+/-<imm8>
429437
* LDRSH<c> <Rt>, [<Rn>, #+/-<imm8>]! *)
@@ -1202,7 +1210,8 @@ let parse_load_store_imm_type
12021210
let imm12 = b 11 0 in
12031211
let imm = TR.tget_ok (mk_arm_immediate_op false 4 (mkNumerical imm12)) in
12041212
let offset = ARMImmOffset imm12 in
1205-
let mk_mem = mk_arm_offset_address_op rnreg offset ~isadd ~isindex ~iswback in
1213+
let mk_mem ?(size=4) (mode: arm_operand_mode_t) =
1214+
mk_arm_offset_address_op rnreg offset ~size ~isadd ~isindex ~iswback mode in
12061215
match (b 22 22, b 20 20, (rnval, p, u, w, imm12)) with
12071216

12081217
(* <cc><2>10010<13><rt><--imm12:4-> *) (* PUSH - A2 *)
@@ -1241,15 +1250,15 @@ let parse_load_store_imm_type
12411250

12421251
(* <cc><2>pu1w0<rn><rt><--imm12---> *) (* STRB-imm *)
12431252
| (1, 0, _) ->
1244-
let mem = mk_mem WR in
1253+
let mem = mk_mem ~size:1 WR in
12451254
(* STRB<c> <Rt>, [<Rn>{, #+/-<imm12>}] Offset: (index,wback) = (T,F)
12461255
* STRB<c> <Rt>, [<Rn>, #+/-<imm12>]! Pre-x : (index,wback) = (T,T)
12471256
* STRB<c> <Rt>, [<Rn>], #+/-<imm12> Post-x: (index,wback) = (F,T) *)
12481257
StoreRegisterByte (c, rt RD, rn, imm, mem, false)
12491258

12501259
(* <cc><2>pu1w1<rn><rt><--imm12---> *) (* LDRB-imm *)
12511260
| (1, 1, _) ->
1252-
let mem = mk_mem RD in
1261+
let mem = mk_mem ~size:1 RD in
12531262
(* LDRB<c> <Rt>, [<Rn>{, #+/-<imm12>}] Offset: (index,wback) = (T,F)
12541263
* LDRB<c> <Rt>, [<Rn>, #+/-<imm12>]! Pre-x : (index,wback) = (T,T)
12551264
* LDRB<c> <Rt>, [<Rn>], #+/-<imm12> Post-x: (index,wback) = (F,T) *)
@@ -1282,7 +1291,8 @@ let parse_load_store_reg_type (instr: doubleword_int) (cond: int) =
12821291
let (shift_t, shift_n) = decode_imm_shift (b 6 5) (b 11 7) in
12831292
let reg_srt = ARMImmSRT (shift_t, shift_n) in
12841293
let offset = arm_shifted_index_offset (get_arm_reg (b 3 0)) reg_srt in
1285-
let mk_mem = mk_arm_offset_address_op rnreg offset ~isadd ~isindex ~iswback in
1294+
let mk_mem ?(size=4) (mode: arm_operand_mode_t) =
1295+
mk_arm_offset_address_op rnreg offset ~size ~isadd ~isindex ~iswback mode in
12861296
let selector = (bv 22, bv 20) in
12871297
match selector with
12881298
(* <cc><3>pu0w0<rn><rt><imm>ty0<rm> *) (* STR (register) - A1 *)
@@ -1301,14 +1311,14 @@ let parse_load_store_reg_type (instr: doubleword_int) (cond: int) =
13011311

13021312
(* <cc><3>pu1w0<rn><rt><imm>ty0<rm> *) (* STRB (register) - A1 *)
13031313
| (1, 0) ->
1304-
let mem = mk_mem WR in
1314+
let mem = mk_mem ~size:1 WR in
13051315
(* STRB<c> <Rt>, [<Rn>,+/-<Rm>{, <shift>}]{!} *)
13061316
(* STRB<c> <Rt>, [<Rn>],+/-<Rm>{, <shift>} *)
13071317
StoreRegisterByte (c, rt RD, rn, rm, mem, false)
13081318

13091319
(* <cc><3>pu1w1<rn><rt><imm>ty0<rm> *) (* LDRB (register) - A1 *)
13101320
| (1, 1) ->
1311-
let mem = mk_mem RD in
1321+
let mem = mk_mem ~size:1 RD in
13121322
LoadRegisterByte (c, rt WR, rn, rm, mem, false)
13131323

13141324
| _ -> OpInvalid

‎CodeHawk/CHB/bchlibarm32/bCHDisassembleThumbInstruction.ml‎

Lines changed: 31 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -3141,7 +3141,7 @@ let parse_thumb32_31_0
31413141
let offset = arm_shifted_index_offset (get_arm_reg (b 3 0)) reg_srt in
31423142
let mem =
31433143
mk_arm_offset_address_op
3144-
rnreg offset ~isadd:true ~isindex:true ~iswback:false in
3144+
rnreg offset ~size:1 ~isadd:true ~isindex:true ~iswback:false in
31453145
(* STRB<c>.W <Rt>, [<Rn>, <Rm>{, LSL #<imm2>}] *)
31463146
StoreRegisterByte (cc, rt RD, rn RD, rm RD, mem WR, true)
31473147

@@ -3152,7 +3152,8 @@ let parse_thumb32_31_0
31523152
let isindex = (b 10 10) = 1 in
31533153
let isadd = (b 9 9) = 1 in
31543154
let iswback = (b 8 8) = 1 in
3155-
let mem = mk_arm_offset_address_op rnreg offset ~isadd ~isindex ~iswback in
3155+
let mem =
3156+
mk_arm_offset_address_op ~size:1 rnreg offset ~isadd ~isindex ~iswback in
31563157
(* STRB<c> <Rt>, [<Rn>, #-<imm8>]
31573158
STRB<c> <Rt>, [<Rn>], #+/-<imm8>
31583159
STRB<c> <Rt>, [<Rn>, #+/-<imm8>]! *)
@@ -3199,7 +3200,7 @@ let parse_thumb32_31_0
31993200
let offset = arm_shifted_index_offset (get_arm_reg (b 3 0)) reg_srt in
32003201
let mem =
32013202
mk_arm_offset_address_op
3202-
rnreg offset ~isadd:true ~isindex:true ~iswback:false in
3203+
rnreg offset ~size:2 ~isadd:true ~isindex:true ~iswback:false in
32033204
(* STRH<c>.W <Rt>, [<Rn>, <Rm>{, LSL #<imm2>}] *)
32043205
StoreRegisterHalfword (cc, rt RD, rn RD, rm RD, mem WR, true)
32053206

@@ -3209,7 +3210,8 @@ let parse_thumb32_31_0
32093210
let isindex = (b 10 10) = 1 in
32103211
let isadd = (b 9 9) = 1 in
32113212
let iswback = (b 8 8) = 1 in
3212-
let mem = mk_arm_offset_address_op rnreg offset ~isadd ~isindex ~iswback in
3213+
let mem =
3214+
mk_arm_offset_address_op ~size:2 rnreg offset ~isadd ~isindex ~iswback in
32133215
(* STRH<c> <Rt>, [<Rn>, #-<imm8>]
32143216
STRH<c> <Rt>, [<Rn>], #+/-<imm8>
32153217
STRH<c> <Rt>, [<Rn>, #+/-<imm8>]! *)
@@ -3222,7 +3224,7 @@ let parse_thumb32_31_0
32223224
let offset = arm_shifted_index_offset (get_arm_reg (b 3 0)) reg_srt in
32233225
let mem =
32243226
mk_arm_offset_address_op
3225-
rnreg offset ~isadd:true ~isindex:true ~iswback:false in
3227+
rnreg offset ~size:2 ~isadd:true ~isindex:true ~iswback:false in
32263228
(* LDRH<c>.W <Rt>, [<Rn>, <Rm>{, LSL #<imm2>}] *)
32273229
LoadRegisterHalfword (cc, rt WR, rn RD, rm RD, mem RD, true)
32283230

@@ -3234,7 +3236,7 @@ let parse_thumb32_31_0
32343236
let iswback = (b 8 8) = 1 in
32353237
let imm = arm_immediate_op (TR.tget_ok (signed_immediate_from_int (b 7 0))) in
32363238
let mem =
3237-
mk_arm_offset_address_op rnreg offset ~isadd ~isindex ~iswback in
3239+
mk_arm_offset_address_op ~size:2 rnreg offset ~isadd ~isindex ~iswback in
32383240
(* LDRH<c>.W <Rt>, [<Rn>{, #+/-<imm8>}] Offset: (index,wback) = (T,F)
32393241
* LDRH<c>.W <Rt>, [<Rn>, #+/-<imm8>]! Pre-x : (index,wback) = (T,T)
32403242
* LDRH<c>.W <Rt>, [<Rn>], #+/-<imm8> Post-x: (index,wback) = (F,T) *)
@@ -3319,7 +3321,7 @@ let parse_thumb32_31_0
33193321
TR.tget_ok (mk_arm_immediate_op false 4 (mkNumerical (b 11 0))) in
33203322
let mem =
33213323
mk_arm_offset_address_op
3322-
rnreg offset ~isadd:true ~isindex:true ~iswback:false in
3324+
rnreg offset ~size:1 ~isadd:true ~isindex:true ~iswback:false in
33233325
StoreRegisterByte (cc, rt RD, rn RD, immop, mem WR, true)
33243326

33253327
(* < 31>00010W1<rn><15><--imm12---> PLD (immediate, T1) *)
@@ -3345,15 +3347,15 @@ let parse_thumb32_31_0
33453347
(* STRH<c>.W <Rt>, [<Rn>, #<imm12>] *)
33463348
let mem =
33473349
mk_arm_offset_address_op
3348-
rnreg offset ~isadd:true ~isindex:true ~iswback:false in
3350+
rnreg offset ~size:2 ~isadd:true ~isindex:true ~iswback:false in
33493351
StoreRegisterHalfword (cc, rt RD, rn RD, rm RD, mem WR, true)
33503352

33513353
(* < 31>00< 11><rn><rt><--imm12---> LDRH (immediate) - T2 *)
33523354
| 11 ->
33533355
(* LDRH<c>.W <Rt>, [<Rn>{, #<imm12>} *)
33543356
let mem =
33553357
mk_arm_offset_address_op
3356-
rnreg offset ~isadd:true ~isindex:true ~iswback:false in
3358+
rnreg offset ~size:2 ~isadd:true ~isindex:true ~iswback:false in
33573359
LoadRegisterHalfword (cc, rt WR, rn RD, rm RD, mem RD, true)
33583360

33593361
(* < 31>00< 12><rn><rt><--imm12---> STR (immediate) - T3 *)
@@ -3395,7 +3397,7 @@ let parse_thumb32_31_0
33953397
let offset = arm_shifted_index_offset rmreg reg_srt in
33963398
let memi =
33973399
mk_arm_offset_address_op
3398-
rnreg offset ~align:1 ~isadd:true ~isindex:true ~iswback:false in
3400+
rnreg offset ~size:1 ~align:1 ~isadd:true ~isindex:true ~iswback:false in
33993401
(* LDRSB<c>.W, <Rt>, [<Rn>, <Rm>{, LSL #<imm2>}] *)
34003402
LoadRegisterSignedByte (cc, rt WR, rn RD, rm RD, memi RD, true)
34013403

@@ -3408,7 +3410,8 @@ let parse_thumb32_31_0
34083410
let imm =
34093411
arm_immediate_op (TR.tget_ok (signed_immediate_from_int (b 7 0))) in
34103412
let mem =
3411-
mk_arm_offset_address_op ~align:1 rnreg offset ~isadd ~isindex ~iswback in
3413+
mk_arm_offset_address_op
3414+
~size:1 ~align:1 rnreg offset ~isadd ~isindex ~iswback in
34123415
(* LDRSB<c> <Rt>, [<Rn>, #-<imm8>]
34133416
LDRSB<c> <Rt>, [<Rn>], #+/-<imm8>
34143417
LDRSB<c> <Rt>, [<Rn>, #+/-<imm8>]! *)
@@ -3532,7 +3535,7 @@ let parse_thumb32_31_0
35323535
let offset = arm_shifted_index_offset rmreg reg_srt in
35333536
let memi =
35343537
mk_arm_offset_address_op
3535-
rnreg offset ~align:1 ~isadd:true ~isindex:true ~iswback:false in
3538+
rnreg offset ~size:2 ~align:2 ~isadd:true ~isindex:true ~iswback:false in
35363539
(* LDRSH<c>.W, <Rt>, [<Rn>, <Rm>{, LSL #<imm2>}] *)
35373540
LoadRegisterSignedHalfword (cc, rt WR, rn RD, rm RD, memi RD, true)
35383541

@@ -3545,7 +3548,8 @@ let parse_thumb32_31_0
35453548
let imm =
35463549
arm_immediate_op (TR.tget_ok (signed_immediate_from_int (b 7 0))) in
35473550
let mem =
3548-
mk_arm_offset_address_op ~align:1 rnreg offset ~isadd ~isindex ~iswback in
3551+
mk_arm_offset_address_op
3552+
~size:2 ~align:2 rnreg offset ~isadd ~isindex ~iswback in
35493553
(* LDRSH<c> <Rt>, [<Rn>, #-<imm8>]
35503554
LDRSH<c> <Rt>, [<Rn>], #+/-<imm8>
35513555
LDRSH<c> <Rt>, [<Rn>, #+/-<imm8>]! *)
@@ -3558,7 +3562,7 @@ let parse_thumb32_31_0
35583562
let offset = ARMImmOffset imm12 in
35593563
let mem =
35603564
mk_arm_offset_address_op
3561-
rnreg offset ~align:1 ~isadd:true ~isindex:true ~iswback:false in
3565+
rnreg offset ~size:2 ~align:1 ~isadd:true ~isindex:true ~iswback:false in
35623566
(* LDRSB<c> <Rt>, [<Rn>, #<imm12>] *)
35633567
LoadRegisterSignedByte (cc, rt WR, rn RD, imm, mem RD, false)
35643568

@@ -3737,7 +3741,7 @@ let parse_thumb32_31_0
37373741
let offset = ARMImmOffset imm12 in
37383742
let mem =
37393743
mk_arm_offset_address_op
3740-
rnreg offset ~align:1 ~isadd:true ~isindex:true ~iswback:false in
3744+
rnreg offset ~size:2 ~align:2 ~isadd:true ~isindex:true ~iswback:false in
37413745
(* LDRSH<c> <Rt>, [<Rn>, #<imm12>] *)
37423746
LoadRegisterSignedHalfword (cc, rt WR, rn RD, imm, mem RD, false)
37433747

@@ -5288,9 +5292,9 @@ let parse_t16_load_store_reg
52885292
let rt = regop rtreg in
52895293
let reg_srt = ARMImmSRT (SRType_LSL, 0) in
52905294
let offset = arm_shifted_index_offset rmreg reg_srt in
5291-
let mem ?(size=4) m =
5295+
let mem ?(size=4) (mode: arm_operand_mode_t) =
52925296
mk_arm_offset_address_op
5293-
~size rnreg offset ~isadd:true ~isindex:true ~iswback:false m in
5297+
~size rnreg offset ~isadd:true ~isindex:true ~iswback:false mode in
52945298

52955299
match (b 11 9) with
52965300

@@ -5302,17 +5306,17 @@ let parse_t16_load_store_reg
53025306
(* 0101001<r><r><r> STRH (register) - T1 *)
53035307
| 1 ->
53045308
(* STRH<c> <Rt>, [<Rn>, <Rm>] *)
5305-
StoreRegisterHalfword (cc, rt RD, rn RD, rm RD, mem WR, false)
5309+
StoreRegisterHalfword (cc, rt RD, rn RD, rm RD, mem ~size:2 WR, false)
53065310

53075311
(* 0101010<r><r><r> STRB (register) - T1 *)
53085312
| 2 ->
53095313
(* STRB<c> <Rt>, [<Rn>, <Rm>] *)
5310-
StoreRegisterByte (cc, rt RD, rn RD, rm RD, mem WR, false)
5314+
StoreRegisterByte (cc, rt RD, rn RD, rm RD, mem ~size:1 WR, false)
53115315

53125316
(* 0101011<r><r><r> LDRSB (register) - T1 *)
53135317
| 3 ->
53145318
(* LDRSB<c> <Rt>, [<Rn>, <Rm>] *)
5315-
LoadRegisterSignedByte (cc, rt WR, rn RD, rm RD, mem RD, false)
5319+
LoadRegisterSignedByte (cc, rt WR, rn RD, rm RD, mem ~size:1 RD, false)
53165320

53175321
(* 0101100<r><r><r> LDR (register) - T1 *)
53185322
| 4 ->
@@ -5332,7 +5336,7 @@ let parse_t16_load_store_reg
53325336
(* 0101111<r><r><r> LDRSH (register) - T1 *)
53335337
| 7 ->
53345338
(* LDRSH<c> <Rt>, [<Rn>, <Rm>] *)
5335-
LoadRegisterSignedHalfword (cc, rt WR, rn RD, rm RD, mem RD, false)
5339+
LoadRegisterSignedHalfword (cc, rt WR, rn RD, rm RD, mem ~size:2 RD, false)
53365340

53375341
| tag -> NotRecognized ("t16_load_store_reg:" ^ (stri tag), instr)
53385342

@@ -5370,16 +5374,16 @@ let parse_t16_load_store_imm
53705374
arm_immediate_op
53715375
(TR.tget_ok (signed_immediate_from_int (mult * (b 10 6)))) in
53725376
let offset (m:int) = ARMImmOffset (m * (b 10 6)) in
5373-
let mem (mult: int) m =
5377+
let mem (mult: int) ?(size=4) (mode: arm_operand_mode_t) =
53745378
mk_arm_offset_address_op
5375-
rnreg (offset mult) ~isadd:true ~isindex:true ~iswback:false m in
5379+
rnreg (offset mult) ~size ~isadd:true ~isindex:true ~iswback:false mode in
53765380

53775381
match (b 12 11) with
53785382
(* 10000<imm><r><r> STRH (immediate) - T1 *)
53795383
| 0 when hw ->
53805384
let immop = imm 2 in
53815385
(* STRH<c> <Rt>, [<Rn>, #<imm>] *)
5382-
StoreRegisterHalfword (cc, rt RD, rn RD, immop, mem 2 WR, false)
5386+
StoreRegisterHalfword (cc, rt RD, rn RD, immop, mem 2 ~size:2 WR, false)
53835387

53845388
(* 01100<imm><r><r> STR (immediate) - T1 *)
53855389
| 0 ->
@@ -5391,7 +5395,7 @@ let parse_t16_load_store_imm
53915395
| 1 when hw ->
53925396
let immop = imm 2 in
53935397
(* LDRH<c> <Rt>, [<Rn>, #<imm>] - T1 *)
5394-
LoadRegisterHalfword (cc, rt WR, rn RD, immop, mem 2 RD, false)
5398+
LoadRegisterHalfword (cc, rt WR, rn RD, immop, mem 2 ~size:2 RD, false)
53955399

53965400
(* 01101<imm><r><r> LDR (immediate) - T1 *)
53975401
| 1 ->
@@ -5403,13 +5407,13 @@ let parse_t16_load_store_imm
54035407
| 2 ->
54045408
let immop = imm 1 in
54055409
(* STRB<c> <Rt>, [<Rn>, #<imm5>] *)
5406-
StoreRegisterByte (cc, rt RD, rn RD, immop, mem 1 WR, false)
5410+
StoreRegisterByte (cc, rt RD, rn RD, immop, mem 1 ~size:1 WR, false)
54075411

54085412
(* 01111<imm><r><r> LDRB (immediate) - T1*)
54095413
| 3 ->
54105414
let immop = imm 1 in
54115415
(* LDRB<c> <Rt>, [<Rn>, #<imm5>] *)
5412-
LoadRegisterByte (cc, rt WR, rn RD, immop, mem 1 RD, false)
5416+
LoadRegisterByte (cc, rt WR, rn RD, immop, mem 1 ~size:1 RD, false)
54135417

54145418
| tag -> NotRecognized ("t16_load_store_imm:" ^ (stri tag), instr)
54155419

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