Programming Language : VHDL
Developer Tool : Xilinx Vivado
It was a final lab and a group project for the CS-1050 Computer Organization and Digital Design module offered by the Department of Computer Science & Engineering, University of Moratuwa in the 2nd semester of Batch 20.
Two different designs were created during the project.
Optimized Design : Design that only satisfies the functional requirements of the lab.
Extra Features Added Design : Extended design capable of Run two different sets of instructions hardcoded in two different Program ROMs. Also, It can control all four segments of seven segment display and can show some extra flags of the Arithmetic Logic Unit(ALU).
Whole details about the project such as,
1. Lab Task
2. Optimized Design Primitives and Slice Logic
3. Additional features and optimizations to design
4. Specific Instructions for operating the machine
5. Conclusion
6. Individual contributions of each group member
7. Component source codes, Test bench codes, Timing Diagram & Schematics
are included in Nano_Processor_Design_Competition_Final_Report.pdf
Bit stream files which are included in BitStream_Files.rar
can be tested on a BASYS3 FPGA Board with the help of Section-04 : Specific Instructions for operating the machine of Nano_Processor_Design_Competition_Final_Report.pdf