Implement transceiver delay compensation configuration

[liamkinne]

Tested on an STM32G474, working up to 10 Mbit/s. Without this, the controller won't ack any frames above 3 Mbit/s.

[richardeoin]

Thanks for the PR! Cool that it's working up to 10 Mbit/s

[liamkinne]

@richardeoin Do you want it to be a bit-and like tdc & 0x7F or an assert to enforce the range?

[richardeoin]

I'd recommend using saturating_mul for the multiplication, followed by core::cmp::min to limit it to 128.

[liamkinne]

@richardeoin looking at the STCubeG4 implementation it looks like the TDCO value is written directly to the register with no need for offsetting by -1.

I assume this is because zero is a valid value unlike dtseg1, dtseg2, etc where it is not.

[richardeoin]

The smallest possible result from btr.dtseg1() * btr.dbrp() is 1. As zero is a valid value, a minus one is needed to ever write 0 to the TDCO field.

[liamkinne]

I can see where you're coming from. I'm just not able to find any evidence in other implementations that this is the case.

This example is where I got the calculation from.

The implementation just writes the value straight to the register without any offsetting of the value.

Sorry to be a pain about this. I just want to make sure it's correct because it's not arbitrarily configurable.

[richardeoin]

I can also merge it like this. In practice +1 or -1 on the value of TDCO won't make a difference to the receiver.

Btw you merged the latest master into the branch of this PR. Typically you would rebase this branch onto master, instead of the merge. That way the changes from the other PR aren't included here. Not a major issue though :)

[liamkinne]

@richardeoin thanks. I've fixed up the commit history.