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update PAC version
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@dotcypress
dotcypress committed Apr 8, 2024
1 parent 7a348ed commit 2d433f6
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Showing 19 changed files with 337 additions and 338 deletions.
74 changes: 37 additions & 37 deletions src/analog/adc.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -118,7 +118,7 @@ impl Adc {
// Enable ADC clocks
ADC::enable(rcc);

adc.cr.modify(|_, w| w.advregen().set_bit());
adc.cr().modify(|_, w| w.advregen().set_bit());

Self {
rb: adc,
Expand All @@ -134,12 +134,12 @@ impl Adc {
match clock_source {
ClockSource::Pclk(div) => self
.rb
.cfgr2
.cfgr2()
.modify(|_, w| unsafe { w.ckmode().bits(div as u8) }),
ClockSource::Async(div) => {
self.rb.cfgr2.modify(|_, w| unsafe { w.ckmode().bits(0) });
self.rb.cfgr2().modify(|_, w| unsafe { w.ckmode().bits(0) });
self.rb
.ccr
.ccr()
.modify(|_, w| unsafe { w.presc().bits(div as u8) });
}
}
Expand All @@ -152,8 +152,8 @@ impl Adc {
///
/// Do not call if an ADC reading is ongoing.
pub fn calibrate(&mut self) {
self.rb.cr.modify(|_, w| w.adcal().set_bit());
while self.rb.cr.read().adcal().bit_is_set() {}
self.rb.cr().modify(|_, w| w.adcal().set_bit());
while self.rb.cr().read().adcal().bit_is_set() {}
}

/// Returns the calibration factors used by the ADC
Expand All @@ -166,7 +166,7 @@ impl Adc {
/// Note that VDDA changes and to a lesser extent temperature changes affect the ADC operating conditions and
/// calibration should be run again for the best accuracy.
pub fn get_calibration(&self) -> CalibrationFactor {
CalibrationFactor(self.rb.calfact.read().calfact().bits())
CalibrationFactor(self.rb.calfact().read().calfact().bits())
}

/// Writes the calibration factors used by the ADC
Expand All @@ -176,7 +176,7 @@ impl Adc {
/// Do not call if an ADC reading is ongoing.
pub fn set_calibration(&mut self, calfact: CalibrationFactor) {
self.rb
.calfact
.calfact()
.write(|w| unsafe { w.calfact().bits(calfact.0) });
}

Expand All @@ -198,34 +198,34 @@ impl Adc {
/// The nuber of bits, the oversampling result is shifted in bits at the end of oversampling
pub fn set_oversampling_shift(&mut self, nrbits: u8) {
self.rb
.cfgr2
.cfgr2()
.modify(|_, w| unsafe { w.ovss().bits(nrbits) });
}

/// Oversampling of adc
pub fn set_oversampling_ratio(&mut self, ratio: OversamplingRatio) {
self.rb
.cfgr2
.cfgr2()
.modify(|_, w| unsafe { w.ovsr().bits(ratio as u8) });
}

pub fn oversampling_enable(&mut self, enable: bool) {
self.rb.cfgr2.modify(|_, w| w.ovse().bit(enable));
self.rb.cfgr2().modify(|_, w| w.ovse().bit(enable));
}

pub fn start_injected(&mut self) {
self.rb.cr.modify(|_, w| w.adstart().set_bit());
self.rb.cr().modify(|_, w| w.adstart().set_bit());
// ADSTART bit is cleared to 0 bevor using this function
// enable self.rb.isr.eos() flag is set after each converstion
self.rb.ier.modify(|_, w| w.eocie().set_bit()); // end of sequence interupt enable
self.rb.ier().modify(|_, w| w.eocie().set_bit()); // end of sequence interupt enable
}

pub fn stop_injected(&mut self) {
// ?????? or is it reset after each conversion?
// ADSTART bit is cleared to 0 bevor using this function
// disable EOS interrupt
// maybe self.rb.cr.adstp().set_bit() must be performed before interrupt is disabled + wait abortion
self.rb.ier.modify(|_, w| w.eocie().clear_bit()); // end of sequence interupt disable
// maybe self.rb.cr().adstp().set_bit() must be performed before interrupt is disabled + wait abortion
self.rb.ier().modify(|_, w| w.eocie().clear_bit()); // end of sequence interupt disable
}

pub fn read_voltage<PIN: Channel<Adc, ID = u8>>(
Expand Down Expand Up @@ -263,15 +263,15 @@ impl Adc {
}

fn power_up(&mut self) {
self.rb.isr.modify(|_, w| w.adrdy().set_bit());
self.rb.cr.modify(|_, w| w.aden().set_bit());
while self.rb.isr.read().adrdy().bit_is_clear() {}
self.rb.isr().modify(|_, w| w.adrdy().set_bit());
self.rb.cr().modify(|_, w| w.aden().set_bit());
while self.rb.isr().read().adrdy().bit_is_clear() {}
}

fn power_down(&mut self) {
self.rb.cr.modify(|_, w| w.addis().set_bit());
self.rb.isr.modify(|_, w| w.adrdy().set_bit());
while self.rb.cr.read().aden().bit_is_set() {}
self.rb.cr().modify(|_, w| w.addis().set_bit());
self.rb.isr().modify(|_, w| w.adrdy().set_bit());
while self.rb.cr().read().aden().bit_is_set() {}
}
}

Expand Down Expand Up @@ -300,10 +300,10 @@ where

fn prepare_injected(&mut self, _pin: &mut PIN, triger_source: InjTrigSource) {
self.rb
.cfgr1
.cfgr1()
.modify(|_, w| unsafe { w.exten().bits(1).extsel().bits(triger_source as u8) });

self.rb.cfgr1.modify(|_, w| unsafe {
self.rb.cfgr1().modify(|_, w| unsafe {
w.res() // set ADC resolution bits (ADEN must be =0)
.bits(self.precision as u8)
.align() // set alignment bit is (ADSTART must be 0)
Expand All @@ -313,7 +313,7 @@ where
self.power_up();

self.rb
.smpr // set sampling time set 1 (ADSTART must be 0)
.smpr() // set sampling time set 1 (ADSTART must be 0)
.modify(|_, w| unsafe { w.smp1().bits(self.sample_time as u8) });

todo!();
Expand All @@ -335,17 +335,17 @@ impl DmaMode<Adc> for Adc {

fn dma_enable(&mut self, enable: bool) {
if enable {
self.rb.cfgr1.modify(|_, w| w.dmaen().set_bit()); // enable dma beeing called
self.rb.cfgr1().modify(|_, w| w.dmaen().set_bit()); // enable dma beeing called
} else {
self.rb.cfgr1.modify(|_, w| w.dmaen().clear_bit()); // disable dma beeing called
self.rb.cfgr1().modify(|_, w| w.dmaen().clear_bit()); // disable dma beeing called
}
}

fn dma_circualr_mode(&mut self, enable: bool) {
if enable {
self.rb.cfgr1.modify(|_, w| w.dmacfg().set_bit()); // activate circular mode
self.rb.cfgr1().modify(|_, w| w.dmacfg().set_bit()); // activate circular mode
} else {
self.rb.cfgr1.modify(|_, w| w.dmacfg().clear_bit()); // disable circular mode
self.rb.cfgr1().modify(|_, w| w.dmacfg().clear_bit()); // disable circular mode
}
}
}
Expand All @@ -359,26 +359,26 @@ where

fn read(&mut self, _pin: &mut PIN) -> nb::Result<WORD, Self::Error> {
self.power_up();
self.rb.cfgr1.modify(|_, w| unsafe {
self.rb.cfgr1().modify(|_, w| unsafe {
w.res()
.bits(self.precision as u8)
.align()
.bit(self.align == Align::Left)
});

self.rb
.smpr
.smpr()
.modify(|_, w| unsafe { w.smp1().bits(self.sample_time as u8) });

self.rb
.chselr0()
.modify(|_, w| unsafe { w.bits(1 << PIN::channel()) });

self.rb.isr.modify(|_, w| w.eos().set_bit());
self.rb.cr.modify(|_, w| w.adstart().set_bit());
while self.rb.isr.read().eos().bit_is_clear() {}
self.rb.isr().modify(|_, w| w.eos().set_bit());
self.rb.cr().modify(|_, w| w.adstart().set_bit());
while self.rb.isr().read().eos().bit_is_clear() {}

let res = self.rb.dr.read().bits() as u16;
let res = self.rb.dr().read().bits() as u16;
let val = if self.align == Align::Left && self.precision == Precision::B_6 {
res << 8
} else {
Expand All @@ -401,15 +401,15 @@ macro_rules! int_adc {
}

pub fn enable(&mut self, adc: &mut Adc) {
adc.rb.ccr.modify(|_, w| w.$en().set_bit());
adc.rb.ccr().modify(|_, w| w.$en().set_bit());
}

pub fn disable(&mut self, adc: &mut Adc) {
adc.rb.ccr.modify(|_, w| w.$en().clear_bit());
adc.rb.ccr().modify(|_, w| w.$en().clear_bit());
}

pub fn enabled(&self, adc: &Adc) -> bool {
adc.rb.ccr.read().$en().bit_is_set()
adc.rb.ccr().read().$en().bit_is_set()
}
}

Expand Down
17 changes: 8 additions & 9 deletions src/crc.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,6 @@
use crate::rcc::{Enable, Rcc, Reset};
use crate::stm32::CRC;
use core::hash::Hasher;
use core::{cell, ptr};

/// Extension trait to constrain the CRC peripheral.
pub trait CrcExt {
Expand Down Expand Up @@ -119,9 +118,9 @@ impl Config {
Some(BitReversal::ByWord) => 0b11,
};

crc.init.write(|w| unsafe { w.crc_init().bits(init) });
crc.pol.write(|w| unsafe { w.bits(poly) });
crc.cr.write(|w| unsafe {
crc.init().write(|w| unsafe { w.crc_init().bits(init) });
crc.pol().write(|w| unsafe { w.bits(poly) });
crc.cr().write(|w| unsafe {
w.rev_in()
.bits(in_rev_bits)
.polysize()
Expand Down Expand Up @@ -149,7 +148,7 @@ impl Crc {
pub fn reset(&mut self) {
let crc = unsafe { &(*CRC::ptr()) };

crc.cr.modify(|_, w| w.reset().set_bit());
crc.cr().modify(|_, w| w.reset().set_bit());
}

/// This will reset the CRC to its initial condition, however with a specific initial value.
Expand All @@ -160,9 +159,9 @@ impl Crc {
pub fn reset_with_inital_value(&mut self, initial_value: u32) {
let crc = unsafe { &(*CRC::ptr()) };

crc.init
crc.init()
.write(|w| unsafe { w.crc_init().bits(initial_value) });
crc.cr.modify(|_, w| w.reset().set_bit());
crc.cr().modify(|_, w| w.reset().set_bit());
}

/// Feed the CRC with data
Expand All @@ -171,7 +170,7 @@ impl Crc {
let crc = unsafe { &(*CRC::ptr()) };
for byte in data {
unsafe {
ptr::write_volatile(cell::UnsafeCell::raw_get(&crc.dr as *const _ as _), byte)
crc.dr().write(|w| w.bits(*byte as _));
}
}
}
Expand All @@ -193,7 +192,7 @@ impl Crc {
pub fn peek_result(&self) -> u32 {
let crc = unsafe { &(*CRC::ptr()) };

crc.dr.read().bits()
crc.dr().read().bits()
}
}

Expand Down
26 changes: 13 additions & 13 deletions src/exti.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -68,21 +68,21 @@ impl ExtiExt for EXTI {
let mask = 1 << line;
match edge {
SignalEdge::Rising => {
self.rtsr1.modify(|r, w| unsafe { w.bits(r.bits() | mask) });
self.rtsr1().modify(|r, w| unsafe { w.bits(r.bits() | mask) });
}
SignalEdge::Falling => {
self.ftsr1.modify(|r, w| unsafe { w.bits(r.bits() | mask) });
self.ftsr1().modify(|r, w| unsafe { w.bits(r.bits() | mask) });
}
SignalEdge::All => {
self.rtsr1.modify(|r, w| unsafe { w.bits(r.bits() | mask) });
self.ftsr1.modify(|r, w| unsafe { w.bits(r.bits() | mask) });
self.rtsr1().modify(|r, w| unsafe { w.bits(r.bits() | mask) });
self.ftsr1().modify(|r, w| unsafe { w.bits(r.bits() | mask) });
}
}
self.wakeup(ev);
}

fn wakeup(&self, ev: Event) {
self.imr1
self.imr1()
.modify(|r, w| unsafe { w.bits(r.bits() | 1 << ev as u8) });
}

Expand All @@ -91,10 +91,10 @@ impl ExtiExt for EXTI {

let line = ev as u8;
let mask = !(1 << line);
self.imr1.modify(|r, w| unsafe { w.bits(r.bits() & mask) });
self.imr1().modify(|r, w| unsafe { w.bits(r.bits() & mask) });
if line <= TRIGGER_MAX {
self.rtsr1.modify(|r, w| unsafe { w.bits(r.bits() & mask) });
self.ftsr1.modify(|r, w| unsafe { w.bits(r.bits() & mask) });
self.rtsr1().modify(|r, w| unsafe { w.bits(r.bits() & mask) });
self.ftsr1().modify(|r, w| unsafe { w.bits(r.bits() & mask) });
}
}

Expand All @@ -105,19 +105,19 @@ impl ExtiExt for EXTI {
}
let mask = 1 << line;
match edge {
SignalEdge::Rising => self.rpr1.read().bits() & mask != 0,
SignalEdge::Falling => self.fpr1.read().bits() & mask != 0,
SignalEdge::Rising => self.rpr1().read().bits() & mask != 0,
SignalEdge::Falling => self.fpr1().read().bits() & mask != 0,
SignalEdge::All => {
(self.rpr1.read().bits() & mask != 0) && (self.fpr1.read().bits() & mask != 0)
(self.rpr1().read().bits() & mask != 0) && (self.fpr1().read().bits() & mask != 0)
}
}
}

fn unpend(&self, ev: Event) {
let line = ev as u8;
if line <= TRIGGER_MAX {
self.rpr1.modify(|_, w| unsafe { w.bits(1 << line) });
self.fpr1.modify(|_, w| unsafe { w.bits(1 << line) });
self.rpr1().modify(|_, w| unsafe { w.bits(1 << line) });
self.fpr1().modify(|_, w| unsafe { w.bits(1 << line) });
}
}
}
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