add STM32L433RC, STM32L433RB and STM32L443RC support

README.md

@@ -641,6 +641,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
 | :green_heart:  | STM32L433CBT<br>STM32L433CCT | Generic Board | *2.1.0* |  |
 | :green_heart:  | STM32L433CBU<br>STM32L433CCU | Generic Board | *2.1.0* |  |
 | :green_heart:  | STM32L443CC<br>STM32L443CC | Generic Board | *2.1.0* |  |
+| :yellow_heart:  | STM32L433RC<br>STM32L443RC<br>STM32L433RB | Generic Board | **2.6.0** |  |
 | :green_heart:  | STM32L433RC-P | Generic Board | *2.0.0* |  |
 | :green_heart:  | STM32L452RC<br>STM32L452RE<br>STM32L462RE | Generic Board | *2.0.0* |  |
 | :green_heart:  | STM32L452RE | [Leafony AP03](https://docs.leafony.com/en/docs/leaf/processor/ap03) | *2.4.0* |

boards.txt

@@ -9239,6 +9239,78 @@ GenL4.menu.pnum.GENERIC_L433CCUX.build.board=GENERIC_L433CCUX
 GenL4.menu.pnum.GENERIC_L433CCUX.build.product_line=STM32L433xx
 GenL4.menu.pnum.GENERIC_L433CCUX.build.variant=STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)
 
+# Generic L433RBIx
+GenL4.menu.pnum.GENERIC_L433RBIX=Generic L433RBIx
+GenL4.menu.pnum.GENERIC_L433RBIX.upload.maximum_size=131072
+GenL4.menu.pnum.GENERIC_L433RBIX.upload.maximum_data_size=65536
+GenL4.menu.pnum.GENERIC_L433RBIX.build.board=GENERIC_L433RBIX
+GenL4.menu.pnum.GENERIC_L433RBIX.build.product_line=STM32L433xx
+GenL4.menu.pnum.GENERIC_L433RBIX.build.variant=STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)
+
+# Generic L433RCIx
+GenL4.menu.pnum.GENERIC_L433RCIX=Generic L433RCIx
+GenL4.menu.pnum.GENERIC_L433RCIX.upload.maximum_size=262144
+GenL4.menu.pnum.GENERIC_L433RCIX.upload.maximum_data_size=65536
+GenL4.menu.pnum.GENERIC_L433RCIX.build.board=GENERIC_L433RCIX
+GenL4.menu.pnum.GENERIC_L433RCIX.build.product_line=STM32L433xx
+GenL4.menu.pnum.GENERIC_L433RCIX.build.variant=STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)
+
+# Generic L433RBTx
+GenL4.menu.pnum.GENERIC_L433RBTX=Generic L433RBTx
+GenL4.menu.pnum.GENERIC_L433RBTX.upload.maximum_size=131072
+GenL4.menu.pnum.GENERIC_L433RBTX.upload.maximum_data_size=65536
+GenL4.menu.pnum.GENERIC_L433RBTX.build.board=GENERIC_L433RBTX
+GenL4.menu.pnum.GENERIC_L433RBTX.build.product_line=STM32L433xx
+GenL4.menu.pnum.GENERIC_L433RBTX.build.variant=STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)
+
+# Generic L433RCTx
+GenL4.menu.pnum.GENERIC_L433RCTX=Generic L433RCTx
+GenL4.menu.pnum.GENERIC_L433RCTX.upload.maximum_size=262144
+GenL4.menu.pnum.GENERIC_L433RCTX.upload.maximum_data_size=65536
+GenL4.menu.pnum.GENERIC_L433RCTX.build.board=GENERIC_L433RCTX
+GenL4.menu.pnum.GENERIC_L433RCTX.build.product_line=STM32L433xx
+GenL4.menu.pnum.GENERIC_L433RCTX.build.variant=STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)
+
+# Generic L433RBYx
+GenL4.menu.pnum.GENERIC_L433RBYX=Generic L433RBYx
+GenL4.menu.pnum.GENERIC_L433RBYX.upload.maximum_size=131072
+GenL4.menu.pnum.GENERIC_L433RBYX.upload.maximum_data_size=65536
+GenL4.menu.pnum.GENERIC_L433RBYX.build.board=GENERIC_L433RBYX
+GenL4.menu.pnum.GENERIC_L433RBYX.build.product_line=STM32L433xx
+GenL4.menu.pnum.GENERIC_L433RBYX.build.variant=STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)
+
+# Generic L433RCYx
+GenL4.menu.pnum.GENERIC_L433RCYX=Generic L433RCYx
+GenL4.menu.pnum.GENERIC_L433RCYX.upload.maximum_size=262144
+GenL4.menu.pnum.GENERIC_L433RCYX.upload.maximum_data_size=65536
+GenL4.menu.pnum.GENERIC_L433RCYX.build.board=GENERIC_L433RCYX
+GenL4.menu.pnum.GENERIC_L433RCYX.build.product_line=STM32L433xx
+GenL4.menu.pnum.GENERIC_L433RCYX.build.variant=STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)
+
+# Generic L443RCIx
+GenL4.menu.pnum.GENERIC_L443RCIX=Generic L443RCIx
+GenL4.menu.pnum.GENERIC_L443RCIX.upload.maximum_size=262144
+GenL4.menu.pnum.GENERIC_L443RCIX.upload.maximum_data_size=65536
+GenL4.menu.pnum.GENERIC_L443RCIX.build.board=GENERIC_L443RCIX
+GenL4.menu.pnum.GENERIC_L443RCIX.build.product_line=STM32L443xx
+GenL4.menu.pnum.GENERIC_L443RCIX.build.variant=STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)
+
+# Generic L443RCTx
+GenL4.menu.pnum.GENERIC_L443RCTX=Generic L443RCTx
+GenL4.menu.pnum.GENERIC_L443RCTX.upload.maximum_size=262144
+GenL4.menu.pnum.GENERIC_L443RCTX.upload.maximum_data_size=65536
+GenL4.menu.pnum.GENERIC_L443RCTX.build.board=GENERIC_L443RCTX
+GenL4.menu.pnum.GENERIC_L443RCTX.build.product_line=STM32L443xx
+GenL4.menu.pnum.GENERIC_L443RCTX.build.variant=STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)
+
+# Generic L443RCYx
+GenL4.menu.pnum.GENERIC_L443RCYX=Generic L443RCYx
+GenL4.menu.pnum.GENERIC_L443RCYX.upload.maximum_size=262144
+GenL4.menu.pnum.GENERIC_L443RCYX.upload.maximum_data_size=65536
+GenL4.menu.pnum.GENERIC_L443RCYX.build.board=GENERIC_L443RCYX
+GenL4.menu.pnum.GENERIC_L443RCYX.build.product_line=STM32L443xx
+GenL4.menu.pnum.GENERIC_L443RCYX.build.variant=STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)
+
 # Generic L433RCTxP
 GenL4.menu.pnum.GENERIC_L433RCTXP=Generic L433RCTxP
 GenL4.menu.pnum.GENERIC_L433RCTXP.upload.maximum_size=262144

variants/STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/generic_clock.c

@@ -24,8 +24,53 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = 0;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = 1;
+  RCC_OscInitStruct.PLL.PLLN = 40;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+    Error_Handler();
+  }
+
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */

variants/STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/ldscript.ld

@@ -0,0 +1,186 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32L433RCTx Device from STM32L4 series
+**                      256Kbytes FLASH
+**                      64Kbytes RAM
+**                      16Kbytes RAM2
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2023 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET,   LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}