variant(H5): add generic H503RB and Nucelo H503RB

README.md

@@ -125,6 +125,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
 | :green_heart:  | STM32G0B1RE | [Nucleo G0B1RE](https://www.st.com/en/evaluation-tools/nucleo-g0b1re.html) | *2.1.0* |  |
 | :green_heart:  | STM32G431RB | [Nucleo G431RB](https://www.st.com/en/evaluation-tools/nucleo-g431rb.html) | *1.7.0* |  |
 | :green_heart:  | STM32G474RE | [Nucleo G474RE](https://www.st.com/en/evaluation-tools/nucleo-g474re.html) | *1.7.0* |  |
+| :yellow_heart:  | STM32H503RB | [Nucleo H503RB](https://www.st.com/en/evaluation-tools/nucleo-h503rb.html) | **2.7.0** |  |
 | :green_heart:  | STM32L010RB | [Nucleo L010RB](https://www.st.com/en/evaluation-tools/nucleo-l010rb.html) | *2.1.0* |  |
 | :green_heart:  | STM32L053R8 | [Nucleo L053R8](http://www.st.com/en/evaluation-tools/nucleo-l053r8.html) | *0.1.0* |  |
 | :green_heart:  | STM32L073RZ | [Nucleo L073RZ](http://www.st.com/en/evaluation-tools/nucleo-l073rz.html) | *1.4.0* |  |
@@ -521,6 +522,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
 
 | Status | Device(s) | Name | Release | Notes |
 | :----: | :-------: | ---- | :-----: | :---- |
+| :yellow_heart:  | STM32H503RB | Generic Board | **2.7.0** |  |
 | :green_heart:  | STM32H563IIKxQ | Generic Board | *2.6.0* |  |
 | :green_heart:  | STM32H563ZG<br>STM32H563ZI | Generic Board | *2.6.0* |  |
 | :green_heart:  | STM32H573IIKxQ | Generic Board | *2.6.0* |  |

boards.txt

@@ -488,6 +488,19 @@ Nucleo_64.menu.pnum.NUCLEO_G474RE.build.series=STM32G4xx
 Nucleo_64.menu.pnum.NUCLEO_G474RE.build.product_line=STM32G474xx
 Nucleo_64.menu.pnum.NUCLEO_G474RE.build.variant=STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET
 
+# NUCLEO H503RB
+Nucleo_64.menu.pnum.NUCLEO_H503RB=Nucleo H503RB
+Nucleo_64.menu.pnum.NUCLEO_H503RB.node=NOD_H503RB
+Nucleo_64.menu.pnum.NUCLEO_H503RB.upload.maximum_size=131072
+Nucleo_64.menu.pnum.NUCLEO_H503RB.upload.maximum_data_size=32768
+Nucleo_64.menu.pnum.NUCLEO_H503RB.build.mcu=cortex-m33
+Nucleo_64.menu.pnum.NUCLEO_H503RB.build.fpu=-mfpu=fpv4-sp-d16
+Nucleo_64.menu.pnum.NUCLEO_H503RB.build.float-abi=-mfloat-abi=hard
+Nucleo_64.menu.pnum.NUCLEO_H503RB.build.board=NUCLEO_H503RB
+Nucleo_64.menu.pnum.NUCLEO_H503RB.build.series=STM32H5xx
+Nucleo_64.menu.pnum.NUCLEO_H503RB.build.product_line=STM32H503xx
+Nucleo_64.menu.pnum.NUCLEO_H503RB.build.variant=STM32H5xx/H503RBT
+
 # NUCLEO_L010RB board
 Nucleo_64.menu.pnum.NUCLEO_L010RB=Nucleo L010RB
 Nucleo_64.menu.pnum.NUCLEO_L010RB.node=NODE_L010RB
@@ -7204,6 +7217,14 @@ GenH5.build.flash_offset=0x0
 GenH5.upload.maximum_size=0
 GenH5.upload.maximum_data_size=0
 
+# Generic H503RBTx
+GenH5.menu.pnum.GENERIC_H503RBTX=Generic H503RBTx
+GenH5.menu.pnum.GENERIC_H503RBTX.upload.maximum_size=131072
+GenH5.menu.pnum.GENERIC_H503RBTX.upload.maximum_data_size=32768
+GenH5.menu.pnum.GENERIC_H503RBTX.build.board=GENERIC_H503RBTX
+GenH5.menu.pnum.GENERIC_H503RBTX.build.product_line=STM32H503xx
+GenH5.menu.pnum.GENERIC_H503RBTX.build.variant=STM32H5xx/H503RBT
+
 # Generic H563IIKxQ
 GenH5.menu.pnum.GENERIC_H563IIKXQ=Generic H563IIKxQ
 GenH5.menu.pnum.GENERIC_H563IIKXQ.upload.maximum_size=2097152

cmake/boards_db.cmake

@@ -71230,6 +71230,91 @@ target_compile_options(GENERIC_G4A1VETX_xusb_HSFS INTERFACE
   "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
 )
 
+# GENERIC_H503RBTX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_H503RBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H503RBT")
+set(GENERIC_H503RBTX_MAXSIZE 131072)
+set(GENERIC_H503RBTX_MAXDATASIZE 32768)
+set(GENERIC_H503RBTX_MCU cortex-m33)
+set(GENERIC_H503RBTX_FPCONF "-")
+add_library(GENERIC_H503RBTX INTERFACE)
+target_compile_options(GENERIC_H503RBTX INTERFACE
+  "SHELL:-DSTM32H503xx  "
+  "SHELL:"
+  "SHELL:"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H503RBTX_MCU}
+)
+target_compile_definitions(GENERIC_H503RBTX INTERFACE
+  "STM32H5xx"
+	"ARDUINO_GENERIC_H503RBTX"
+	"BOARD_NAME=\"GENERIC_H503RBTX\""
+	"BOARD_ID=GENERIC_H503RBTX"
+	"VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_H503RBTX INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H5xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/
+  ${GENERIC_H503RBTX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_H503RBTX INTERFACE
+  "LINKER:--default-script=${GENERIC_H503RBTX_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=131072"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=32768"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H503RBTX_MCU}
+)
+target_link_libraries(GENERIC_H503RBTX INTERFACE
+  arm_ARMv8MMLlfsp_math
+)
+
+add_library(GENERIC_H503RBTX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_H503RBTX_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H503RBTX_serial_generic INTERFACE)
+target_compile_options(GENERIC_H503RBTX_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_H503RBTX_serial_none INTERFACE)
+target_compile_options(GENERIC_H503RBTX_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_H503RBTX_usb_CDC INTERFACE)
+target_compile_options(GENERIC_H503RBTX_usb_CDC INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_H503RBTX_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_H503RBTX_usb_CDCgen INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_H503RBTX_usb_HID INTERFACE)
+target_compile_options(GENERIC_H503RBTX_usb_HID INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_H503RBTX_usb_none INTERFACE)
+target_compile_options(GENERIC_H503RBTX_usb_none INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H503RBTX_xusb_FS INTERFACE)
+target_compile_options(GENERIC_H503RBTX_xusb_FS INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H503RBTX_xusb_HS INTERFACE)
+target_compile_options(GENERIC_H503RBTX_xusb_HS INTERFACE
+  "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_H503RBTX_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_H503RBTX_xusb_HSFS INTERFACE
+  "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
 # GENERIC_H563IIKXQ
 # -----------------------------------------------------------------------------
 
@@ -98518,6 +98603,91 @@ target_compile_options(NUCLEO_G474RE_xusb_HSFS INTERFACE
   "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
 )
 
+# NUCLEO_H503RB
+# -----------------------------------------------------------------------------
+
+set(NUCLEO_H503RB_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H503RBT")
+set(NUCLEO_H503RB_MAXSIZE 131072)
+set(NUCLEO_H503RB_MAXDATASIZE 32768)
+set(NUCLEO_H503RB_MCU cortex-m33)
+set(NUCLEO_H503RB_FPCONF "fpv4-sp-d16-hard")
+add_library(NUCLEO_H503RB INTERFACE)
+target_compile_options(NUCLEO_H503RB INTERFACE
+  "SHELL:-DSTM32H503xx  "
+  "SHELL:"
+  "SHELL:"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${NUCLEO_H503RB_MCU}
+)
+target_compile_definitions(NUCLEO_H503RB INTERFACE
+  "STM32H5xx"
+	"ARDUINO_NUCLEO_H503RB"
+	"BOARD_NAME=\"NUCLEO_H503RB\""
+	"BOARD_ID=NUCLEO_H503RB"
+	"VARIANT_H=\"variant_NUCLEO_H503RB.h\""
+)
+target_include_directories(NUCLEO_H503RB INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H5xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/
+  ${NUCLEO_H503RB_VARIANT_PATH}
+)
+
+target_link_options(NUCLEO_H503RB INTERFACE
+  "LINKER:--default-script=${NUCLEO_H503RB_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=131072"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=32768"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${NUCLEO_H503RB_MCU}
+)
+target_link_libraries(NUCLEO_H503RB INTERFACE
+
+)
+
+add_library(NUCLEO_H503RB_serial_disabled INTERFACE)
+target_compile_options(NUCLEO_H503RB_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(NUCLEO_H503RB_serial_generic INTERFACE)
+target_compile_options(NUCLEO_H503RB_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(NUCLEO_H503RB_serial_none INTERFACE)
+target_compile_options(NUCLEO_H503RB_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(NUCLEO_H503RB_usb_CDC INTERFACE)
+target_compile_options(NUCLEO_H503RB_usb_CDC INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(NUCLEO_H503RB_usb_CDCgen INTERFACE)
+target_compile_options(NUCLEO_H503RB_usb_CDCgen INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(NUCLEO_H503RB_usb_HID INTERFACE)
+target_compile_options(NUCLEO_H503RB_usb_HID INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0 -DUSBD_PID=0 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(NUCLEO_H503RB_usb_none INTERFACE)
+target_compile_options(NUCLEO_H503RB_usb_none INTERFACE
+  "SHELL:"
+)
+add_library(NUCLEO_H503RB_xusb_FS INTERFACE)
+target_compile_options(NUCLEO_H503RB_xusb_FS INTERFACE
+  "SHELL:"
+)
+add_library(NUCLEO_H503RB_xusb_HS INTERFACE)
+target_compile_options(NUCLEO_H503RB_xusb_HS INTERFACE
+  "SHELL:-DUSE_USB_HS"
+)
+add_library(NUCLEO_H503RB_xusb_HSFS INTERFACE)
+target_compile_options(NUCLEO_H503RB_xusb_HSFS INTERFACE
+  "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
 # NUCLEO_H563ZI
 # -----------------------------------------------------------------------------
 

variants/STM32H5xx/H503RBT/CMakeLists.txt

@@ -22,6 +22,7 @@ add_library(variant_bin STATIC EXCLUDE_FROM_ALL
   generic_clock.c
   PeripheralPins.c
   variant_generic.cpp
+  variant_NUCLEO_H503RB.cpp
 )
 target_link_libraries(variant_bin PUBLIC variant_usage)
 

variants/STM32H5xx/H503RBT/generic_clock.c

@@ -20,8 +20,55 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
+
+  /* Configure the main internal regulator output voltage */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
+
+  while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+
+  /* Initializes the RCC Oscillators according to the specified parameters
+   * in the RCC_OscInitTypeDef structure.
+   */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_CSI;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.CSIState = RCC_CSI_ON;
+  RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI;
+  RCC_OscInitStruct.PLL.PLLM = 1;
+  RCC_OscInitStruct.PLL.PLLN = 125;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 2;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2;
+  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+  /* Initializes the CPU, AHB and APB buses clocks */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
+                                | RCC_CLOCKTYPE_PCLK3;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /* Initializes the peripherals clock */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB;
+  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+  PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_CSI;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */