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chore(F4): update to latest STM32CubeF4 v1.28.0 #2213

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Nov 29, 2023
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chore(F4): update to latest STM32CubeF4 v1.28.0 #2213

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e268a5a
system(F4) update STM32F4xx HAL Drivers to v1.8.2
fpistm Nov 29, 2023
f79dbe1
system(F4): update STM32F4xx CMSIS Drivers to v2.6.9
fpistm Nov 29, 2023
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24 changes: 12 additions & 12 deletions system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - peripherals registers declarations and bits definition
* - Macros to access peripheral’s registers hardware
* - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
Expand All @@ -34,7 +34,7 @@
#define __STM32F401xC_H

#ifdef __cplusplus
extern "C" {
extern "C" {
#endif /* __cplusplus */

/** @addtogroup Configuration_section_for_CMSIS
Expand Down Expand Up @@ -64,7 +64,7 @@
*/
typedef enum
{
/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
Expand All @@ -73,7 +73,7 @@ typedef enum
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
/****** STM32 specific Interrupt Numbers **********************************************************************/
/****** STM32 specific Interrupt Numbers **********************************************************************/
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
Expand Down Expand Up @@ -129,7 +129,7 @@ typedef enum
I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
FPU_IRQn = 81, /*!< FPU global interrupt */
SPI4_IRQn = 84 /*!< SPI4 global Interrupt */
SPI4_IRQn = 84 /*!< SPI4 global Interrupt */
} IRQn_Type;

/**
Expand Down Expand Up @@ -203,7 +203,7 @@ typedef struct
__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
__IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
__IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
}DBGMCU_TypeDef;
} DBGMCU_TypeDef;


/**
Expand Down Expand Up @@ -822,9 +822,9 @@ typedef struct
* @}
*/

/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/

/******************************************************************************/
/* Peripheral Registers_Bits_Definition */
Expand Down Expand Up @@ -1400,7 +1400,7 @@ typedef struct

/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */


Expand Down Expand Up @@ -3915,7 +3915,7 @@ typedef struct
#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
*/
#define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */

Expand Down Expand Up @@ -4291,7 +4291,7 @@ typedef struct
#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
/******************** Bit definition for RCC_AHB2ENR register ***************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
*/
#define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */

Expand Down
24 changes: 12 additions & 12 deletions system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - peripherals registers declarations and bits definition
* - Macros to access peripheral’s registers hardware
* - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
Expand All @@ -34,7 +34,7 @@
#define __STM32F401xE_H

#ifdef __cplusplus
extern "C" {
extern "C" {
#endif /* __cplusplus */

/** @addtogroup Configuration_section_for_CMSIS
Expand Down Expand Up @@ -64,7 +64,7 @@
*/
typedef enum
{
/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
Expand All @@ -73,7 +73,7 @@ typedef enum
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
/****** STM32 specific Interrupt Numbers **********************************************************************/
/****** STM32 specific Interrupt Numbers **********************************************************************/
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
Expand Down Expand Up @@ -129,7 +129,7 @@ typedef enum
I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
FPU_IRQn = 81, /*!< FPU global interrupt */
SPI4_IRQn = 84 /*!< SPI4 global Interrupt */
SPI4_IRQn = 84 /*!< SPI4 global Interrupt */
} IRQn_Type;

/**
Expand Down Expand Up @@ -203,7 +203,7 @@ typedef struct
__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
__IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
__IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
}DBGMCU_TypeDef;
} DBGMCU_TypeDef;


/**
Expand Down Expand Up @@ -822,9 +822,9 @@ typedef struct
* @}
*/

/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/

/******************************************************************************/
/* Peripheral Registers_Bits_Definition */
Expand Down Expand Up @@ -1400,7 +1400,7 @@ typedef struct

/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */


Expand Down Expand Up @@ -3915,7 +3915,7 @@ typedef struct
#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
*/
#define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */

Expand Down Expand Up @@ -4291,7 +4291,7 @@ typedef struct
#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
/******************** Bit definition for RCC_AHB2ENR register ***************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
*/
#define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */

Expand Down
32 changes: 16 additions & 16 deletions system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - peripherals registers declarations and bits definition
* - Macros to access peripheral’s registers hardware
* - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
Expand All @@ -34,7 +34,7 @@
#define __STM32F405xx_H

#ifdef __cplusplus
extern "C" {
extern "C" {
#endif /* __cplusplus */

/** @addtogroup Configuration_section_for_CMSIS
Expand Down Expand Up @@ -64,7 +64,7 @@
*/
typedef enum
{
/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
Expand All @@ -73,7 +73,7 @@ typedef enum
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
/****** STM32 specific Interrupt Numbers **********************************************************************/
/****** STM32 specific Interrupt Numbers **********************************************************************/
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
Expand Down Expand Up @@ -314,7 +314,7 @@ typedef struct
__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
__IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
__IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
}DBGMCU_TypeDef;
} DBGMCU_TypeDef;


/**
Expand Down Expand Up @@ -1052,9 +1052,9 @@ typedef struct
* @}
*/

/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/

/******************************************************************************/
/* Peripheral Registers_Bits_Definition */
Expand All @@ -1066,7 +1066,7 @@ typedef struct
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
*/
#define ADC_MULTIMODE_SUPPORT /*!<ADC Multimode feature available on specific devices */

Expand Down Expand Up @@ -5327,7 +5327,7 @@ typedef struct

/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */


Expand All @@ -5342,7 +5342,7 @@ typedef struct
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
*/
#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
/******************** Bit definition for DAC_CR register ********************/
Expand Down Expand Up @@ -9181,7 +9181,7 @@ typedef struct
#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
*/
#define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */

Expand Down Expand Up @@ -9629,7 +9629,7 @@ typedef struct
#define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
/******************** Bit definition for RCC_AHB2ENR register ***************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
*/
#define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */

Expand All @@ -9642,7 +9642,7 @@ typedef struct

/******************** Bit definition for RCC_AHB3ENR register ***************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
*/
#define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */

Expand Down Expand Up @@ -10075,7 +10075,7 @@ typedef struct
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
*/
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
#define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
Expand Down Expand Up @@ -14272,7 +14272,7 @@ typedef struct
#define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
#define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
#define FLASH_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
#define FLASH_SCALE2_LATENCY4_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
#define FLASH_SCALE2_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */

#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
#define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
Expand Down
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