updated various code lines due to "fixed predecrement CPU bug"

TODO.txt

@@ -1,28 +1,37 @@
+FINALIZING THE CURRENT "STREAK" of FPGA + Q-TRIS:
+
+* Q-TRIS V1.0: Implement winning the game (>= 1.000 lines), take care that
+  upleveling does not lead to undefined memory locations (table). Optimize
+  some code parts (at least those resulting from the CPU fix).
+
+* Q-TRIS and/or Monitor: Stand alone auto-starting Q-TRIS bitstream. Do it in
+  the most simple form, which is: make it an .org 0x0000 startable executable,
+  move the variables that need to be in RAM via other .org commands. (That
+  means, we need a simple multiplication command outside the monitor.)
+
+* Test Q-TRIS thoroughly again by playing a ~250+ lines session.
+
+* Make a V1.21 release of the hardware and the whole package (and include
+  the Q-TRIS as a stand alone released bitstream)
+
 HARDWARE:
 
-* Fix CPU BUG: Pre-decrement of the destination operand does not work,
-  if the source operand is used directly. But it works, if the source
-  operand is used indirectly. Example:
-    this works:         MOVE @R2, @--R0
-    this does not work: MOVE R2, @--R0
-  The bug will be presumably fixed, by changing
-    and Opcode /= opcMOVE
-  in vhdl/qnice_cpu.vhd line 401 to
-    and (Opcode /= opcMOVE or Dst_Mode = amIndirPreDec) 
-  and therefore making it very similar to line 455: The speed optimization
-  must be disabled in case of pre-decrement.
-  As soon as this is fixed, the fix can be e.g. tested by changing the two
-  spots marked with "@TODO" in test_programs/decimal.asm. As soon as
-  everything works, the code in this test program and also in demos/q-tris.asm
-  needs to be cleaned up accordingly.
-
-* remove ROM and replace by prefilled RAM
+* Remove ROM and replace by prefilled RAM
+
+* Memory management unit (more than 64kWords of RAM/ROM, pages, etc.)
+
+* Interrupt system
+
+* Debugging mechanisms (e.g. single-step mode in hardware)
 
 * Fix tristate problem that slows down CPU by ~50%
 
 * Improve design to support 100 MHz
 
-* keyboard: remove hardcoded hardcoded 18000
+* Keyboard: remove hardcoded hardcoded 18000
+
+* Refactor scancode conversion to be more table/ROM like and less
+  like a huge array of multiplexers
 
 * Add a timer with 0,1us Resolution (10 MHz frequency), so that
   we can measure performance (e.g. against the emulator)
@@ -31,20 +40,20 @@ HARDWARE:
 
 * Refactor TIL and TIL Mask to support 8 digits / 32 bits
 
-* Refactor scancode conversion to be more table/ROM like and less
-  like a huge array of multiplexers
-
 * Refactor Video RAM: avoid inferring two RAMs for video RAM
 
-* single-step-mode in hardware incl. address/data display on 7-segs
+* VGA being able to report the vertical retrace for flicker-free graphics,
+  e.g. for being able to enhance Q-TRIS to work double-buffered and to
+  switch buffers during retrace. And/or for having a good general sync.
+  mechanism. To "report" via register and/or interrupt.
 
 MONITOR and/or STANDARD LIBs:
 
 * Backspace and CTRL-U support in IO$GETS
 
-* Basic mathematical routines * (exists), / (from decimal.asm), % (ditto)
+* Basic mathematical routines * (exists), / (from decimal.asm?), % (ditto?)
 
-* Decimal converter (from decimal.asm)
+* Decimal converter (from decimal.asm?)
 
 * 32 bit arithmetic
 

demos/q-tris.asm

@@ -149,7 +149,7 @@ CAH_X       .EQU 41
 CAH_Y       .EQU 8
 CAH_W       .EQU 40
 CAH_H       .EQU 10
-CRE_A_HELP  .ASCII_W "Q-TRIS V0.9 by sy2002 in January 2016   "
+CRE_A_HELP  .ASCII_W "Q-TRIS V0.9 by sy2002 in February 2016  "
             .ASCII_W "                                        "
             .ASCII_W "How to play:                            "
             .ASCII_W "                                        "
@@ -419,11 +419,11 @@ HANDLE_STATS    INCRB
                 ; the level is multipled to account for the higher difficulty
                 ; in higher levels
 _H_STATS_SCORE  MOVE    R8, R9                 
-                SYSCALL(mult, 1)
+                SYSCALL(mult, 1)                ; @TODO: replace SYSCALLs
                 MOVE    R10, R8
                 MOVE    Level, R9
                 MOVE    @R9, R9
-                SYSCALL(mult, 1)
+                SYSCALL(mult, 1)                ; @TODO: replace SYSCALLs
                 MOVE    Score, R0
                 ADD     R10, @R0
 
@@ -1761,6 +1761,8 @@ PAINT_DIGIT     INCRB
 
                 INCRB
 
+                ; @TODO: replace SYSCALLs, so that Q-Tris can run as
+                ; stand alone "app" independendly from the monitor
                 MOVE    DIGITS_WPD, R9          ; calculate offset for digit
                 SYSCALL(mult, 1)                ; pattern: R8 x DIGITS_WPD
 
@@ -1867,15 +1869,13 @@ MAKE_DECIMAL    INCRB
 
 _MD_LOOP        MOVE    R4, R9                  ; divide by 10
                 RSUB    DIV_AND_MODULO, 1       ; R8 = "shrinked" dividend
-                SUB     1, R0                   ; @TODO: PREDECREMENT CPU BUG!
-                MOVE    R9, @R0                 ; extract current digit place
+                MOVE    R9, @--R0               ; extract current digit place
                 CMP     R5, R8                  ; done?
                 RBRA    _MD_LOOP, !Z            ; no: next iteration
 
 _MD_LEADING_0   CMP     R7, R0                  ; enough leading "0" there?
                 RBRA    _MD_RET, Z              ; yes: return
-                SUB     1, R0                   ; @TODO: PREDECREMENT CPU BUG!
-                MOVE    0, @R0                  ; no: add a "0" digit
+                MOVE    0, @--R0                ; no: add a "0" digit
                 RBRA    _MD_LEADING_0, 1
 
 _MD_RET         MOVE    R6, R8                  ; restore R8 & R9

pore/boot_message.asm

@@ -2,4 +2,4 @@ PORE$NEWLINE  .ASCII_W "\n"
 
 ; PORE$RESETMSG .ASCII_W "QNICE-FPGA [WIP] [only 16 reg-banks!] by sy2002 in January 2016 (GIT #"
 
-PORE$RESETMSG .ASCII_W "QNICE-FPGA Version 1.2 by sy2002 in January 2016 (GIT COMMIT #d52cb2e)\n"
+PORE$RESETMSG .ASCII_W "QNICE-FPGA Version 1.21 by sy2002 in February 2016 (GIT COMMIT #8e368ed)\n"

pore/boot_message.txt

@@ -2,4 +2,4 @@ PORE$NEWLINE  .ASCII_W "\n"
 
 ; PORE$RESETMSG .ASCII_W "QNICE-FPGA [WIP] [only 16 reg-banks!] by sy2002 in January 2016 (GIT #"
 
-PORE$RESETMSG .ASCII_W "QNICE-FPGA Version 1.2 by sy2002 in January 2016 (GIT COMMIT #
+PORE$RESETMSG .ASCII_W "QNICE-FPGA Version 1.21 by sy2002 in February 2016 (GIT COMMIT #

test_programs/decimal.asm

@@ -83,15 +83,13 @@ MAKE_DECIMAL    INCRB
 
 _MD_LOOP        MOVE    R4, R9                  ; divide by 10
                 RSUB    DIV_AND_MODULO, 1       ; R8 = "shrinked" dividend
-                SUB     1, R0                   ; @TODO: PREDECREMENT CPU BUG!
-                MOVE    R9, @R0                 ; extract current digit place
+                MOVE    R9, @--R0               ; extract current digit place
                 CMP     R5, R8                  ; done?
                 RBRA    _MD_LOOP, !Z            ; no: next iteration
 
 _MD_LEADING_0   CMP     R7, R0                  ; enough leading "0" there?
                 RBRA    _MD_RET, Z              ; yes: return
-                SUB     1, R0                   ; @TODO: PREDECREMENT CPU BUG!
-                MOVE    0, @R0                  ; no: add a "0" digit
+                MOVE    0, @--R0                ; no: add a "0" digit
                 RBRA    _MD_LEADING_0, 1
 
 _MD_RET         MOVE    R6, R8                  ; restore R8 & R9

vhdl/env1_globals.vhd

@@ -11,11 +11,11 @@ package env1_globals is
 
 -- file name and file size (in lines) of the file that is converted to the ROM located at 0x0000
 constant ROM_FILE             : string    := "../monitor/monitor.rom";
-constant ROM_SIZE             : natural   := 2838;
+constant ROM_SIZE             : natural   := 2840;
 
 -- file name of file and file size (in lines) of the file containing the Power On & Reset Execution (PORE) ROM
 constant PORE_ROM_FILE        : string    := "../pore/pore.rom";
-constant PORE_ROM_SIZE        : natural   := 455;
+constant PORE_ROM_SIZE        : natural   := 457;
 
 -- size of lower register bank: should be 256
 -- set to 16 during development for faster synthesis, routing, etc.