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month update in PORE and monitor and minor documentation updates
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sy2002 committed Nov 8, 2020
1 parent 83aed0d commit b150b08
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2 changes: 2 additions & 0 deletions VERSIONS.txt
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Expand Up @@ -14,6 +14,8 @@ WIP sift through all issues tagged with V1.7 that tackle ISA changes
taking two CPU cycles. This leads to an average speed of 13.21 MIPS, which
is a speed-up of 2% compared to V1.6. The new peak performance is 14.67 MIPS
which is an improvement of 8% compared to V1.6.
<plus two more refactorings: non-taken branches in 1 cycle, INCRB/DECRB in
1 cycle; more speed; see MIPS.md>
TODO: <WASM emulator Website needs to name the new speed, and for better
reading, we should print the speed in bold on the website, as the
user needs to adjust the emulation speed manually.>
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4 changes: 2 additions & 2 deletions doc/MIPS.md
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Expand Up @@ -4,13 +4,13 @@ QNICE-FPGA Performance Characteristics
* The system runs with 50 MHz on all currently supported hardware targets.

* The CPU is built around a variable-length state machine. This means that
there are instructions that are as short as two clock cycles and others that
there are instructions that are as short as one clock cycle and others that
are in general as long as six clock cycles.

* Slow RAM, ROM and peripheral devices can make the execution even longer, as
they are able to add wait-states to the CPU's execution.

* It is therefore difficult, to measure "The" CPU performance in MIPS
* It is therefore difficult, to exactly measure "The" CPU performance in MIPS
(Million Instructions Per Second). In contrast, it always depends on the
workload that is being executed.

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2 changes: 1 addition & 1 deletion monitor/qmon.asm
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Expand Up @@ -625,7 +625,7 @@ QMON$LOAD_E1C SUB IO$HEX_NIBBLES, R10 ; get numeric representation of
;* Strings
;***************************************************************************************
QMON$WELCOME .ASCII_P "\n\nSimple QNICE-monitor - Version 1.7 (Bernd Ulmann, sy2002, September 2020)\n"
QMON$WELCOME .ASCII_P "\n\nSimple QNICE-monitor - Version 1.7 (Bernd Ulmann, sy2002, November 2020)\n"
#ifdef RAM_MONITOR
.ASCII_P "Running in RAM!\n"
#endif
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2 changes: 1 addition & 1 deletion pore/boot_message.txt
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Expand Up @@ -4,4 +4,4 @@ PORE$NEWLINE .ASCII_W "\n\n"

; PORE$RESETMSG .ASCII_W "QNICE-FPGA Version 1.7 by sy2002 & MJoergen in September 2020 (GIT #"

PORE$RESETMSG .ASCII_W "QNICE-FPGA V1.7 [WIP] by sy2002 & MJoergen in September 2020 (GIT #
PORE$RESETMSG .ASCII_W "QNICE-FPGA V1.7 [WIP] by sy2002 & MJoergen in November 2020 (GIT #
2 changes: 1 addition & 1 deletion pore/boot_message_mega65.txt
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Expand Up @@ -4,4 +4,4 @@ PORE$NEWLINE .ASCII_W "\n\n"

; PORE$RESETMSG .ASCII_W "QNICE-FPGA @ MEGA65 Version 1.7 by sy2002 & MJoergen in September 2020 (GIT #"

PORE$RESETMSG .ASCII_W "QNICE-FPGA @ MEGA65 V1.7 [WIP] by sy2002 & MJoergen in September 2020 (GIT #
PORE$RESETMSG .ASCII_W "QNICE-FPGA @ MEGA65 V1.7 [WIP] by sy2002 & MJoergen in November 2020 (GIT #

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