[snippy]: Randomize rounding modes for OPERAND_FRMARG

llvm/test/tools/llvm-snippy/floating-point/float-different-rounding-modes.yaml

@@ -0,0 +1,24 @@
+# RUN: llvm-snippy %s | FileCheck %s
+
+include:
+  - ../Inputs/sections.yaml
+options:
+  march: riscv64-unknown-elf
+  mcpu: generic-rv64
+  mattr: "+f"
+  num-instrs: 200
+  dump-mf: true
+histogram:
+  - [FADD_S, 1.0]
+
+# COM: RNE - 0b000
+# COM: RTZ - 0b001
+# COM: RDN - 0b010
+# COM: RUP - 0b011
+# COM: RMM - 0b100
+
+# CHECK-DAG: [[REG:\$f[[:digit:]]+_f]] = FADD_S {{.*}}, 0
+# CHECK-DAG: [[REG:\$f[[:digit:]]+_f]] = FADD_S {{.*}}, 1
+# CHECK-DAG: [[REG:\$f[[:digit:]]+_f]] = FADD_S {{.*}}, 2
+# CHECK-DAG: [[REG:\$f[[:digit:]]+_f]] = FADD_S {{.*}}, 3
+# CHECK-DAG: [[REG:\$f[[:digit:]]+_f]] = FADD_S {{.*}}, 4

llvm/tools/llvm-snippy/lib/Target/RISCV/Target.cpp

@@ -2486,8 +2486,21 @@ class SnippyRISCVTarget final : public SnippyTarget {
       snippy::fatal("AVL operand generation is not supported. Probably "
                     "snippy still does "
                     "not support vector instructions generation.");
-    case RISCVOp::OPERAND_FRMARG:
-      return MachineOperand::CreateImm(0);
+    case RISCVOp::OPERAND_FRMARG: {
+      // Floating-point operations use either a static rounding mode encoded in
+      // the instruction, or a dynamic rounding mode held in frm.
+      // 000 - RNE (Round to Nearest, ties to Even)
+      // 001 - RTZ (Round towards Zero)
+      // 010 - RDN (Round Down)
+      // 011 - RUP (Round Up)
+      // 100 - RMM (Round to Nearest, ties to Max Magnitude)
+      // 101 - <reserved>
+      // 110 - <reserved>
+      // 111 - DYN (In instruction’s rm field, selects dynamic rounding mode)
+      using namespace RISCVFPRndMode;
+      return MachineOperand::CreateImm(
+          snippy::selectFrom(RNE, RTZ, RDN, RUP, RMM));
+    }
     }
   }