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Add PerByteAtomicMaybeUninit (byte-wise atomic memcpy)#54

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taiki-e wants to merge 1 commit intomainfrom
memcpy
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Add PerByteAtomicMaybeUninit (byte-wise atomic memcpy)#54
taiki-e wants to merge 1 commit intomainfrom
memcpy

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@taiki-e taiki-e commented Nov 30, 2025

Closes #1

@taiki-e taiki-e added O-arm Target: 32-bit Arm processors (armv6, armv7, thumb...), including 64-bit Arm in AArch32 state O-riscv Target: RISC-V architecture O-x86 Target: x86/x64 processors O-mips Target: MIPS processors O-powerpc Target: PowerPC processors O-s390x Target: SystemZ processors (s390x) O-loongarch Target: LoongArch O-hexagon Target: Qualcomm Hexagon O-avr Target: AVR O-msp430 Target: MSP430 O-aarch64 Target: Armv8-A, Armv8-R, or later processors in AArch64 mode O-xtensa Target: Xtensa processors O-m68k Target: Motorola 68000 series O-sparc Target: SPARC processors O-csky Target: C-SKY processors labels Nov 30, 2025
@taiki-e taiki-e force-pushed the memcpy branch 4 times, most recently from d298d26 to 4d1916f Compare December 29, 2025 13:16
@taiki-e taiki-e force-pushed the main branch 6 times, most recently from d0bb684 to bfa583b Compare January 14, 2026 10:22
@taiki-e taiki-e force-pushed the main branch 3 times, most recently from 41cd357 to 768529e Compare January 25, 2026 08:54
@taiki-e taiki-e force-pushed the main branch 6 times, most recently from 1498669 to bd7180e Compare January 25, 2026 11:58
@taiki-e taiki-e mentioned this pull request Feb 14, 2026
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O-aarch64 Target: Armv8-A, Armv8-R, or later processors in AArch64 mode O-arm Target: 32-bit Arm processors (armv6, armv7, thumb...), including 64-bit Arm in AArch32 state O-avr Target: AVR O-csky Target: C-SKY processors O-hexagon Target: Qualcomm Hexagon O-loongarch Target: LoongArch O-m68k Target: Motorola 68000 series O-mips Target: MIPS processors O-msp430 Target: MSP430 O-powerpc Target: PowerPC processors O-riscv Target: RISC-V architecture O-s390x Target: SystemZ processors (s390x) O-sparc Target: SPARC processors O-x86 Target: x86/x64 processors O-xtensa Target: Xtensa processors

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raw: atomic load/store on array/slice of primitives

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