Remove xtdc CSRs zcherihybrid extension (riscv#527)

Fixes riscv#519

src/csv/CHERI_CSR.csv

@@ -37,9 +37,6 @@ direct write if address didn't change","✔","","","","Zcmt","Jump Vector Table
 "dddc","0x7bc","","D","DRW","tag=0, otherwise undefined","Apply <<section_invalid_addr_conv>>.
 Always update the CSR with <<SCADDR>> even if the address didn't change.","Apply <<section_invalid_addr_conv>> and update the CSR with the result if the address changed,
 direct write if address didn't change","","✔","","","{cheri_default_ext_name}, Sdext","Debug Default Data Capability (saved/restored on debug mode entry/exit)","","","","","","","","","","","","","","","","","","","","",""
-"mtdc","0x74c","","M","MRW, <<asr_perm>>","tag=0, otherwise undefined","Update the CSR using <<SCADDR>>.","direct write","","","","","{cheri_default_ext_name}, M-mode","Machine Trap Data Capability (scratch register)","","","","","","","","","","","","","","","","","","","","",""
-"stdc","0x163","","S","SRW, <<asr_perm>>","tag=0, otherwise undefined","Update the CSR using <<SCADDR>>.","direct write","","","","","{cheri_default_ext_name}, S-mode","Supervisor Trap Data Capability (scratch register)","","","","","","","","","","","","","","","","","","","","",""
-"vstdc","0x245","","VS","HRW, <<asr_perm>>","tag=0, otherwise undefined","Update the CSR using <<SCADDR>>.","direct write","","","","","{cheri_default_ext_name}, H","Virtual Supervisor Trap Data Capability (scratch register)","","","","","","","","","","","","","","","","","","","","",""
 "ddc","0x416","","U","URW","<<infinite-cap>>","Apply <<section_invalid_addr_conv>>.
 Always update the CSR with <<SCADDR>> even if the address didn't change.","Apply <<section_invalid_addr_conv>> and update the CSR with the result if the address changed,
 direct write if address didn't change","","✔","","","{cheri_default_ext_name}","User Default Data Capability","","","","","","","","","","","","","","","","","","","","",""

src/hypervisor-integration.adoc

@@ -146,22 +146,6 @@ The <<vscause>> register is as defined in cite:[riscv-priv-spec]. It must
 additionally support the new exception code for CHERI exceptions that
 <<scause>> supports.
 
-[#vstdc,reftext="vstdc"]
-=== Virtual Supervisor Trap Default Capability Register (vstdc)
-
-The <<vstdc>> register is a capability width read/write register that is
-VS-mode's version of supervisor register <<stdc>>. This register is only
-present when the implementation supports {cheri_default_ext_name}.
-
-{TAG_RESET_CSR}
-
-{REQUIRE_CRE_CSR}
-
-{REQUIRE_HYBRID_CSR}
-
-.Virtual supervisor trap default capability register
-include::img/vstdcreg.edn[]
-
 [#vstval,reftext="vstval"]
 === Virtual Supervisor Trap Value Register (vstval)
 

src/riscv-hybrid-integration.adoc

@@ -429,22 +429,6 @@ Setting the MBE, SBE, or UBE field to a value that is not the reset value of
 MBE disables most CHERI features and instructions, as described in
 xref:section_cheri_disable[xrefstyle=short], while in that privilege mode.
 
-[#mtdc,reftext="mtdc"]
-==== Machine Trap Default Capability Register (mtdc)
-
-The <<mtdc>> register is a capability width read/write register dedicated
-for use by machine mode. Typically, it is used to hold a data capability to a
-machine-mode hart-local context space, to load into <<ddc>>.
-
-{TAG_RESET_CSR}
-
-{REQUIRE_CRE_CSR}
-
-{REQUIRE_HYBRID_CSR}
-
-.Machine-mode trap data capability register
-include::img/mtdcreg.edn[]
-
 [#mseccfg,reftext="mseccfg"]
 ==== Machine Security Configuration Register (mseccfg)
 
@@ -482,22 +466,6 @@ xref:section_cheri_disable[xrefstyle=short].
 
 The reset value is 0.
 
-[#stdc,reftext="stdc"]
-==== Supervisor Trap Default Capability Register (stdc)
-
-The <<stdc>> register is a capability width read/write register dedicated
-for use by supervisor mode. Typically, it is used to hold a data capability to
-a supervisor-mode hart-local context space, to load into <<ddc>>.
-
-{TAG_RESET_CSR}
-
-{REQUIRE_CRE_CSR}
-
-{REQUIRE_HYBRID_CSR}
-
-.Supervisor trap data capability register (*stdc*)
-include::img/stdcreg.edn[]
-
 [#senvcfg,reftext="senvcfg"]
 ==== Supervisor Environment Configuration Register (senvcfg)