Release/v5.5

components/bootloader_support/src/bootloader_random_esp32c5.c

@@ -11,6 +11,8 @@
 #include "esp_private/regi2c_ctrl.h"
 #include "soc/lpperi_reg.h"
 
+#define I2C_SAR_ADC_INIT_CODE_VAL 2150
+
 void bootloader_random_enable(void)
 {
     adc_ll_reset_register();
@@ -30,8 +32,8 @@ void bootloader_random_enable(void)
     ANALOG_CLOCK_ENABLE();
 
     adc_ll_regi2c_init();
-    adc_ll_set_calibration_param(ADC_UNIT_1, 0x866);
-    adc_ll_set_calibration_param(ADC_UNIT_2, 0x866);
+    adc_ll_set_calibration_param(ADC_UNIT_1, I2C_SAR_ADC_INIT_CODE_VAL);
+    adc_ll_set_calibration_param(ADC_UNIT_2, I2C_SAR_ADC_INIT_CODE_VAL);
 
     adc_digi_pattern_config_t pattern_config = {};
     pattern_config.unit = ADC_UNIT_1;

components/bootloader_support/src/bootloader_random_esp32c6.c

@@ -10,6 +10,8 @@
 #include "hal/adc_types.h"
 #include "esp_private/regi2c_ctrl.h"
 
+#define I2C_SAR_ADC_INIT_CODE_VAL 2150
+
 void bootloader_random_enable(void)
 {
     adc_ll_reset_register();
@@ -29,8 +31,8 @@ void bootloader_random_enable(void)
     ANALOG_CLOCK_ENABLE();
 
     adc_ll_regi2c_init();
-    adc_ll_set_calibration_param(ADC_UNIT_1, 0x866);
-    adc_ll_set_calibration_param(ADC_UNIT_2, 0x866);
+    adc_ll_set_calibration_param(ADC_UNIT_1, I2C_SAR_ADC_INIT_CODE_VAL);
+    adc_ll_set_calibration_param(ADC_UNIT_2, I2C_SAR_ADC_INIT_CODE_VAL);
 
     adc_digi_pattern_config_t pattern_config = {};
     pattern_config.unit = ADC_UNIT_2;

components/bootloader_support/src/bootloader_random_esp32c61.c

@@ -10,6 +10,8 @@
 #include "hal/adc_types.h"
 #include "esp_private/regi2c_ctrl.h"
 
+#define I2C_SAR_ADC_INIT_CODE_VAL 2150
+
 void bootloader_random_enable(void)
 {
     adc_ll_reset_register();
@@ -29,8 +31,8 @@ void bootloader_random_enable(void)
     ANALOG_CLOCK_ENABLE();
 
     adc_ll_regi2c_init();
-    adc_ll_set_calibration_param(ADC_UNIT_1, 0x866);
-    adc_ll_set_calibration_param(ADC_UNIT_2, 0x866);
+    adc_ll_set_calibration_param(ADC_UNIT_1, I2C_SAR_ADC_INIT_CODE_VAL);
+    adc_ll_set_calibration_param(ADC_UNIT_2, I2C_SAR_ADC_INIT_CODE_VAL);
 
     adc_digi_pattern_config_t pattern_config = {};
     pattern_config.unit = ADC_UNIT_1;

components/bootloader_support/src/bootloader_random_esp32h2.c

@@ -10,6 +10,8 @@
 #include "hal/adc_types.h"
 #include "esp_private/regi2c_ctrl.h"
 
+#define I2C_SAR_ADC_INIT_CODE_VAL 2150
+
 void bootloader_random_enable(void)
 {
     adc_ll_reset_register();
@@ -29,8 +31,8 @@ void bootloader_random_enable(void)
     ANALOG_CLOCK_ENABLE();
 
     adc_ll_regi2c_init();
-    adc_ll_set_calibration_param(ADC_UNIT_1, 0x866);
-    adc_ll_set_calibration_param(ADC_UNIT_2, 0x866);
+    adc_ll_set_calibration_param(ADC_UNIT_1, I2C_SAR_ADC_INIT_CODE_VAL);
+    adc_ll_set_calibration_param(ADC_UNIT_2, I2C_SAR_ADC_INIT_CODE_VAL);
 
     adc_digi_pattern_config_t pattern_config = {};
     pattern_config.atten = ADC_ATTEN_DB_2_5;

components/bootloader_support/src/bootloader_random_esp32p4.c

@@ -1,108 +1,88 @@
 /*
  * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
+*
+* SPDX-License-Identifier: Apache-2.0
+*/
+#include "sdkconfig.h"
 #include "bootloader_random.h"
-#include "soc/soc.h"
-#include "soc/adc_reg.h"
-#include "soc/pmu_reg.h"
-#include "soc/regi2c_saradc.h"
-#include "soc/hp_sys_clkrst_reg.h"
-#include "soc/lp_adc_reg.h"
-#include "esp_private/regi2c_ctrl.h"
-#include "esp_rom_regi2c.h"
+#include "hal/regi2c_ctrl_ll.h"
+#include "hal/adc_ll.h"
+#include "hal/adc_types.h"
+#include "hal/config.h"
 
-// TODO IDF-6497: once ADC API is supported, use the API instead of defining functions and constants here
+#include "esp_private/periph_ctrl.h"
+#include "esp_private/adc_share_hw_ctrl.h"
 
-#define I2C_SAR_ADC_INIT_CODE_VAL 2166
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+#include "hal/trng_ll.h"
+#endif
 
-typedef struct {
-    int atten;
-    int channel;
-} pattern_item;
-
-typedef struct {
-    pattern_item item[4];
-} pattern_table;
-
-static void adc1_fix_initcode_set(uint32_t initcode_value)
-{
-    uint32_t msb = initcode_value >> 8;
-    uint32_t lsb = initcode_value & 0xff;
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
-}
-
-//total 4 tables
-static void hpadc_sar1_pattern_table_cfg(unsigned int table_idx, pattern_table table)
-{
-    uint32_t wdata = 0;
-    wdata = (table.item[0].channel << 20 | table.item[0].atten << 18 |
-            table.item[1].channel << 14|table.item[1].atten << 12 |
-            table.item[2].channel << 8 |table.item[2].atten << 6 |
-            table.item[3].channel << 2 |table.item[3].atten);
-    WRITE_PERI_REG(ADC_SAR1_PATT_TAB1_REG + table_idx * 4, wdata);
-}
+#define I2C_SAR_ADC_INIT_CODE_VAL       2166
+#define ADC_RNG_CLKM_DIV_NUM            0
+#define ADC_RNG_CLKM_DIV_B              0
+#define ADC_RNG_CLKM_DIV_A              0
 
 void bootloader_random_enable(void)
 {
-    pattern_table sar1_table[4] = {};
-    uint32_t pattern_len = 0;
-
-    SET_PERI_REG_MASK(HP_SYS_CLKRST_SOC_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_ADC_APB_CLK_EN);
-    SET_PERI_REG_MASK(HP_SYS_CLKRST_PERI_CLK_CTRL23_REG, HP_SYS_CLKRST_REG_ADC_CLK_EN);
+    _adc_ll_reset_register();
+    _adc_ll_enable_bus_clock(true);
 
-    SET_PERI_REG_MASK(RTCADC_MEAS1_MUX_REG, RTCADC_SAR1_DIG_FORCE);
-    SET_PERI_REG_MASK(PMU_RF_PWC_REG,PMU_XPD_PERIF_I2C);
+    adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_XTAL);
+    adc_ll_digi_controller_clk_div(0, 0, 0);
 
-    uint32_t sar1_clk_div_num = GET_PERI_REG_BITS2((HP_SYS_CLKRST_PERI_CLK_CTRL24_REG),
-            (HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM_M),
-            (HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM_S));
-
-    SET_PERI_REG_MASK(ADC_CTRL_REG_REG, ADC_START_FORCE); //start force 1
+    // some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
+#ifndef BOOTLOADER_BUILD
+    regi2c_saradc_enable();
+#else
+    regi2c_ctrl_ll_i2c_sar_periph_enable();
+#endif
 
     // enable analog i2c master clock for RNG runtime
     ANALOG_CLOCK_ENABLE();
 
-    adc1_fix_initcode_set(I2C_SAR_ADC_INIT_CODE_VAL);
-
-    //  cfg pattern table
-    sar1_table[0].item[0].channel = 10; //rand() % 6;
-    sar1_table[0].item[0].atten = 3;
-    sar1_table[0].item[1].channel = 10;
-    sar1_table[0].item[1].atten = 3;
-    sar1_table[0].item[2].channel = 10;
-    sar1_table[0].item[2].atten = 3;
-    sar1_table[0].item[3].channel = 10;
-    sar1_table[0].item[3].atten = 3;
-
-    hpadc_sar1_pattern_table_cfg(0, sar1_table[0]);
-    SET_PERI_REG_BITS(ADC_CTRL_REG_REG, ADC_SAR1_PATT_LEN, pattern_len, ADC_SAR1_PATT_LEN_S);
-
-    SET_PERI_REG_BITS(ADC_CTRL_REG_REG, ADC_XPD_SAR1_FORCE, 3, ADC_XPD_SAR1_FORCE_S);
-    SET_PERI_REG_BITS(ADC_CTRL_REG_REG, ADC_XPD_SAR2_FORCE, 3, ADC_XPD_SAR2_FORCE_S);
-
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_ENT_VDD_GRP1, 1);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_DTEST_VDD_GRP1, 0);
-
-    CLEAR_PERI_REG_MASK(ADC_CTRL_REG_REG, ADC_START_FORCE);
-    SET_PERI_REG_MASK(ADC_CTRL2_REG, ADC_TIMER_EN);
-    SET_PERI_REG_BITS(ADC_CTRL2_REG, ADC_TIMER_TARGET, sar1_clk_div_num * 25, ADC_TIMER_TARGET_S);
-
-    while (GET_PERI_REG_MASK(ADC_INT_RAW_REG, ADC_SAR1_DONE_INT_RAW) == 0) { }
-
-    SET_PERI_REG_MASK(ADC_INT_CLR_REG, ADC_APB_SARADC1_DONE_INT_CLR);
+    adc_ll_regi2c_init();
+    adc_ll_set_calibration_param(ADC_UNIT_1, I2C_SAR_ADC_INIT_CODE_VAL);
+
+    adc_digi_pattern_config_t pattern_config = {};
+    pattern_config.unit = ADC_UNIT_1;
+    pattern_config.atten = ADC_ATTEN_DB_12;
+    pattern_config.channel = ADC_CHANNEL_10;
+    adc_ll_digi_set_pattern_table(ADC_UNIT_1, 0, pattern_config);
+    adc_ll_digi_set_pattern_table(ADC_UNIT_1, 1, pattern_config);
+    adc_ll_digi_set_pattern_table(ADC_UNIT_1, 2, pattern_config);
+    adc_ll_digi_set_pattern_table(ADC_UNIT_1, 3, pattern_config);
+    adc_ll_digi_set_pattern_table_len(ADC_UNIT_1, 1);
+
+    adc_ll_set_controller(ADC_UNIT_1, ADC_LL_CTRL_DIG);
+    adc_ll_digi_set_power_manage(ADC_UNIT_1, ADC_LL_POWER_SW_ON);
+
+    adc_ll_digi_set_clk_div(15);
+    adc_ll_digi_set_trigger_interval(100);
+    adc_ll_digi_trigger_enable();
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+    trng_ll_enable();
+#endif
 }
 
 void bootloader_random_disable(void)
 {
+    adc_ll_digi_trigger_disable();
+    adc_ll_digi_reset_pattern_table();
+    adc_ll_set_calibration_param(ADC_UNIT_1, 0x0);
+    adc_ll_set_calibration_param(ADC_UNIT_2, 0x0);
+    adc_ll_regi2c_adc_deinit();
+
+#ifndef BOOTLOADER_BUILD
+    regi2c_saradc_disable();
+#endif
+
     // disable analog i2c master clock
     ANALOG_CLOCK_DISABLE();
+    adc_ll_digi_controller_clk_div(4, 0, 0);
+    adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_XTAL);
+    adc_ll_set_controller(ADC_UNIT_1, ADC_LL_CTRL_ULP);
 
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, 0);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, 0);
-
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_ENT_VDD_GRP1, 0);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_DTEST_VDD_GRP1, 0);
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+    trng_ll_disable();
+#endif
 }

components/bootloader_support/src/esp32c5/bootloader_esp32c5.c

@@ -43,6 +43,7 @@
 #include "hal/lpwdt_ll.h"
 #include "hal/regi2c_ctrl_ll.h"
 #include "hal/brownout_ll.h"
+#include "hal/axi_icm_ll.h"
 
 static const char *TAG = "boot.esp32c5";
 
@@ -85,6 +86,9 @@ static void bootloader_super_wdt_auto_feed(void)
 
 static inline void bootloader_hardware_init(void)
 {
+    // Clear bit reset_event_bypass to ensure that the system bus is also reset during a core reset (WDT),
+    // preventing bus freezing caused by an incorrect MSPI core reset in ROM.
+    axi_icm_ll_reset_with_core_reset(true);
     _regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
     regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-8667 Remove this?
     regi2c_ctrl_ll_master_configure_clock();

components/bootloader_support/src/esp32c61/bootloader_esp32c61.c

@@ -44,6 +44,7 @@
 #include "hal/lpwdt_ll.h"
 #include "hal/regi2c_ctrl_ll.h"
 #include "hal/brownout_ll.h"
+#include "hal/axi_icm_ll.h"
 
 static const char *TAG = "boot.esp32c61";
 
@@ -86,6 +87,9 @@ static void bootloader_super_wdt_auto_feed(void)
 
 static inline void bootloader_hardware_init(void)
 {
+    // Clear bit reset_event_bypass to ensure that the system bus is also reset during a core reset (WDT),
+    // preventing bus freezing caused by an incorrect MSPI core reset in ROM.
+    axi_icm_ll_reset_with_core_reset(true);
     _regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
     regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-9274 Remove this?
     regi2c_ctrl_ll_master_configure_clock();

components/bt/common/include/bt_common.h

@@ -238,6 +238,7 @@ typedef uint64_t UINT64;
 typedef bool BOOLEAN;
 /* Maximum UUID size - 16 bytes, and structure to hold any type of UUID. */
 #define MAX_UUID_SIZE              16
+#define MAX_UUID_NUM               32
 
 typedef struct {
 #define LEN_UUID_16     2

components/bt/host/bluedroid/bta/dm/bta_dm_act.c

@@ -2056,7 +2056,7 @@ void bta_dm_sdp_result (tBTA_DM_MSG *p_data)
 #endif
 
     UINT32 num_uuids = 0;
-    UINT8  uuid_list[32][MAX_UUID_SIZE]; // assuming a max of 32 services
+    UINT8  uuid_list[MAX_UUID_NUM][MAX_UUID_SIZE]; // assuming a max of MAX_UUID_NUM services
 
     if ((p_data->sdp_event.sdp_result == SDP_SUCCESS)
             || (p_data->sdp_event.sdp_result == SDP_NO_RECS_MATCH)
@@ -2119,8 +2119,12 @@ void bta_dm_sdp_result (tBTA_DM_MSG *p_data)
                             (tBTA_SERVICE_MASK)(BTA_SERVICE_ID_TO_SERVICE_MASK(bta_dm_search_cb.service_index - 1));
                         tmp_svc = bta_service_id_to_uuid_lkup_tbl[bta_dm_search_cb.service_index - 1];
                         /* Add to the list of UUIDs */
-                        sdpu_uuid16_to_uuid128(tmp_svc, uuid_list[num_uuids]);
-                        num_uuids++;
+                        if (num_uuids < MAX_UUID_NUM) {
+                            sdpu_uuid16_to_uuid128(tmp_svc, uuid_list[num_uuids]);
+                            num_uuids++;
+                        } else {
+                            APPL_TRACE_WARNING("only process the first %d records\n", MAX_UUID_NUM);
+                        }
                     }
                 }
             }
@@ -2154,8 +2158,13 @@ void bta_dm_sdp_result (tBTA_DM_MSG *p_data)
                 p_sdp_rec = SDP_FindServiceInDb_128bit(bta_dm_search_cb.p_sdp_db, p_sdp_rec);
                 if (p_sdp_rec) {
                     if (SDP_FindServiceUUIDInRec_128bit(p_sdp_rec, &temp_uuid)) {
-                        memcpy(uuid_list[num_uuids], temp_uuid.uu.uuid128, MAX_UUID_SIZE);
-                        num_uuids++;
+                        if (num_uuids < MAX_UUID_NUM) {
+                            memcpy(uuid_list[num_uuids], temp_uuid.uu.uuid128, MAX_UUID_SIZE);
+                            num_uuids++;
+                        } else {
+                            APPL_TRACE_WARNING("only process the first %d records\n", MAX_UUID_NUM);
+                            break;
+                        }
                     }
                 }
             } while (p_sdp_rec);

components/cxx/test_apps/.build-test-rules.yml

@@ -2,10 +2,6 @@
 
 components/cxx/test_apps:
   enable:
-    - if: IDF_TARGET in ["esp32", "esp32c3"]
+    - if: IDF_TARGET in ["esp32", "esp32c3", "esp32p4"]
       temporary: true
       reason: the other targets are not tested yet
-  disable:
-    - if: IDF_TARGET == "esp32p4"
-      temporary: true
-      reason: p4 rev3 migration # TODO: IDF-14402

components/cxx/test_apps/exception/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C3 |
-| ----------------- | ----- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-P4 |
+| ----------------- | ----- | -------- | -------- |

components/cxx/test_apps/exception/main/test_exception.cpp

@@ -13,7 +13,7 @@
    - 88 bytes are allocated by pthread_setspecific() to init internal lock
    - some more memory...
    */
-#if CONFIG_IDF_TARGET_ESP32
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32P4
 #define LEAKS (300)
 #elif CONFIG_IDF_TARGET_ESP32S2
 #define LEAKS (800)

components/cxx/test_apps/exception/pytest_cxx_exception.py

@@ -6,6 +6,6 @@
 
 
 @pytest.mark.generic
-@idf_parametrize('target', ['esp32', 'esp32c3'], indirect=['target'])
+@idf_parametrize('target', ['esp32', 'esp32c3', 'esp32p4'], indirect=['target'])
 def test_cxx_exception(dut: Dut) -> None:
     dut.run_all_single_board_cases()

components/cxx/test_apps/exception_no_except/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C3 |
-| ----------------- | ----- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-P4 |
+| ----------------- | ----- | -------- | -------- |

components/cxx/test_apps/exception_no_except/pytest_cxx_exception_no_except.py

@@ -6,7 +6,7 @@
 
 
 @pytest.mark.generic
-@idf_parametrize('target', ['esp32', 'esp32c3'], indirect=['target'])
+@idf_parametrize('target', ['esp32', 'esp32c3', 'esp32p4'], indirect=['target'])
 def test_cxx_noexcept_out_of_range(dut: Dut) -> None:
     dut.expect_exact('Press ENTER to see the list of tests')
     dut.write('1')
@@ -15,7 +15,7 @@ def test_cxx_noexcept_out_of_range(dut: Dut) -> None:
 
 
 @pytest.mark.generic
-@idf_parametrize('target', ['esp32', 'esp32c3'], indirect=['target'])
+@idf_parametrize('target', ['esp32', 'esp32c3', 'esp32p4'], indirect=['target'])
 def test_cxx_noexcept_bad_alloc(dut: Dut) -> None:
     dut.expect_exact('Press ENTER to see the list of tests')
     dut.write('2')

components/cxx/test_apps/general/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C3 |
-| ----------------- | ----- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-P4 |
+| ----------------- | ----- | -------- | -------- |