Release/v5.3

components/esp_coex/src/coexist.c

@@ -189,6 +189,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
             {
                 gpio_func_sel(gpio_pin.priority, PIN_FUNC_GPIO);
                 gpio_set_direction(gpio_pin.priority, GPIO_MODE_INPUT);
+                gpio_set_pull_mode(gpio_pin.priority, GPIO_PULLDOWN_ONLY);
                 esp_rom_gpio_connect_in_signal(gpio_pin.priority, EXTERNAL_COEX_SIGNAL_I1_IDX, false);
                 REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.priority), GPIO_PIN1_SYNC1_BYPASS, 2);
                 REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.priority), GPIO_PIN1_SYNC2_BYPASS, 2);
@@ -206,6 +207,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
             {
                 gpio_func_sel(gpio_pin.request, PIN_FUNC_GPIO);
                 gpio_set_direction(gpio_pin.request, GPIO_MODE_INPUT);
+                gpio_set_pull_mode(gpio_pin.request, GPIO_PULLDOWN_ONLY);
                 esp_rom_gpio_connect_in_signal(gpio_pin.request, EXTERNAL_COEX_SIGNAL_I0_IDX, false);
                 REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.request), GPIO_PIN1_SYNC1_BYPASS, 2);
                 REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.request), GPIO_PIN1_SYNC2_BYPASS, 2);
@@ -224,6 +226,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
             {
                 gpio_func_sel(gpio_pin.tx_line, PIN_FUNC_GPIO);
                 gpio_set_direction(gpio_pin.tx_line, GPIO_MODE_INPUT);
+                gpio_set_pull_mode(gpio_pin.tx_line, GPIO_PULLDOWN_ONLY);
                 esp_rom_gpio_connect_in_signal(gpio_pin.tx_line, EXTERNAL_COEX_SIGNAL_I1_IDX, false);
                 REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.tx_line), GPIO_PIN1_SYNC1_BYPASS, 2);
                 REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.tx_line), GPIO_PIN1_SYNC2_BYPASS, 2);
@@ -241,6 +244,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
             {
                 gpio_func_sel(gpio_pin.grant, PIN_FUNC_GPIO);
                 gpio_set_direction(gpio_pin.grant, GPIO_MODE_INPUT);
+                gpio_set_pull_mode(gpio_pin.grant, GPIO_PULLUP_ONLY);
                 esp_rom_gpio_connect_in_signal(gpio_pin.grant, EXTERNAL_COEX_SIGNAL_I0_IDX, false);
                 REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.grant), GPIO_PIN1_SYNC1_BYPASS, 2);
                 REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.grant), GPIO_PIN1_SYNC2_BYPASS, 2);

components/esp_driver_tsens/test_apps/temperature_sensor/pytest_temperature_sensor.py

@@ -1,6 +1,5 @@
-# SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: CC0-1.0
-
 import pytest
 from pytest_embedded import Dut
 from pytest_embedded_idf.unity_tester import CaseTester
@@ -37,9 +36,9 @@ def test_temperature_sensor_cbs(dut: Dut) -> None:
 @pytest.mark.esp32s3
 @pytest.mark.esp32c2
 @pytest.mark.esp32c6
-@pytest.mark.wifi_two_dut
+@pytest.mark.two_duts
 @pytest.mark.parametrize('count', [2], indirect=True)
 def test_temperature_phy_cases(case_tester: CaseTester) -> None:  # type: ignore
     for case in case_tester.test_menu:
-        if case.attributes.get('test_env', 'wifi_two_dut') == 'wifi_two_dut':
+        if case.attributes.get('test_env', 'two_duts') == 'two_duts':
             case_tester.run_all_multi_dev_cases(case=case, reset=True)

components/esp_driver_usb_serial_jtag/src/usb_serial_jtag_vfs.c

@@ -176,6 +176,10 @@ static int usb_serial_jtag_rx_char(int fd)
 
 static ssize_t usb_serial_jtag_write(int fd, const void * data, size_t size)
 {
+    if (!usb_serial_jtag_is_connected()) {
+        // TODO: IDF-14303
+        return -1;
+    }
     const char *data_c = (const char *)data;
     /*  Even though newlib does stream locking on each individual stream, we need
      *  a dedicated lock if two streams (stdout and stderr) point to the
@@ -220,6 +224,10 @@ static void usb_serial_jtag_return_char(int fd, int c)
 
 static ssize_t usb_serial_jtag_read(int fd, void* data, size_t size)
 {
+    if (!usb_serial_jtag_is_connected()) {
+        // TODO: IDF-14303
+        return -1;
+    }
     char *data_c = (char *) data;
     size_t received = 0;
     size_t available_size = 0;
@@ -323,6 +331,10 @@ static int usb_serial_jtag_fcntl(int fd, int cmd, int arg)
 
 static int usb_serial_jtag_fsync(int fd)
 {
+    if (!usb_serial_jtag_is_connected()) {
+        // TODO: IDF-14303
+        return -1;
+    }
     _lock_acquire_recursive(&s_ctx.write_lock);
     usb_serial_jtag_ll_txfifo_flush();
     //Wait for the host to have picked up the buffer, but honour the timeout in

components/esp_hw_support/Kconfig

@@ -129,12 +129,11 @@ menu "Hardware Settings"
 
         config ESP_SLEEP_GPIO_RESET_WORKAROUND
             bool "light sleep GPIO reset workaround"
-            default y if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 || \
-                IDF_TARGET_ESP32C6 || IDF_TARGET_ESP32H2
+            default y if !(IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2)
             select PM_SLP_DISABLE_GPIO if FREERTOS_USE_TICKLESS_IDLE
             help
-                esp32c2, esp32c3, esp32s3, esp32c6 and esp32h2 will reset at wake-up if GPIO is received
-                a small electrostatic pulse during light sleep, with specific condition
+                All existing chips except esp32 and esp32s2 will reset on wake-up if a GPIO receives
+                a small electrostatic pulse during light sleep, with specific conditions.
 
                 - GPIO needs to be configured as input-mode only
                 - The pin receives a small electrostatic pulse, and reset occurs when the pulse

components/esp_hw_support/lowpower/cpu_retention/port/esp32p4/sleep_cpu.c

@@ -402,7 +402,11 @@ static TCM_IRAM_ATTR esp_err_t do_cpu_retention(sleep_cpu_entry_cb_t goto_sleep,
         }
 #endif
 
-        return (*goto_sleep)(wakeup_opt, reject_opt, lslp_mem_inf_fpu, dslp);
+        uint32_t reject =  (*goto_sleep)(wakeup_opt, reject_opt, lslp_mem_inf_fpu, dslp);
+        if (reject) {
+            restore_mstatus(mstatus);
+            return reject;
+        }
     }
 #if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME
     else {

components/esp_hw_support/port/esp32p4/private_include/pmu_param.h

@@ -34,7 +34,7 @@ extern "C" {
 // FOR LIGHTSLEEP
 #define PMU_HP_DRVB_LIGHTSLEEP      0
 #define PMU_LP_DRVB_LIGHTSLEEP      0
-#define PMU_HP_XPD_LIGHTSLEEP       1
+#define PMU_HP_XPD_LIGHTSLEEP       0 // Always use DCDC power supply in lightsleep
 
 #define PMU_DBG_ATTEN_LIGHTSLEEP_DEFAULT    0
 #define PMU_HP_DBIAS_LIGHTSLEEP_0V6 1

components/esp_hw_support/sleep_modes.c

@@ -1020,13 +1020,11 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
             /* On esp32c6, only the lp_aon pad hold function can only hold the GPIO state in the active mode.
                In order to avoid the leakage of the SPI cs pin, hold it here */
 #if (CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND)
-#if !CONFIG_IDF_TARGET_ESP32H2 // ESP32H2 TODO IDF-7359
             if(!(pd_flags & RTC_SLEEP_PD_VDDSDIO)) {
                 /* Cache suspend also means SPI bus IDLE, then we can hold SPI CS pin safely */
                 gpio_ll_hold_en(&GPIO, SPI_CS0_GPIO_NUM);
             }
 #endif
-#endif
 
 #if SOC_PMU_SUPPORTED
 #if SOC_PM_CPU_RETENTION_BY_SW && ESP_SLEEP_POWER_DOWN_CPU
@@ -1049,11 +1047,9 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
 
             /* Unhold the SPI CS pin */
 #if (CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND)
-#if !CONFIG_IDF_TARGET_ESP32H2 // ESP32H2 TODO IDF-7359
             if(!(pd_flags & RTC_SLEEP_PD_VDDSDIO)) {
                 gpio_ll_hold_dis(&GPIO, SPI_CS0_GPIO_NUM);
             }
-#endif
 #endif
             /* Cache Resume 1: Resume cache for continue running*/
             resume_cache();
@@ -2456,7 +2452,7 @@ static uint32_t get_power_down_flags(void)
 #endif
 
 #if SOC_PM_SUPPORT_CNNT_PD
-    if (s_config.domain[ESP_PD_DOMAIN_CNNT].pd_option != ESP_PD_OPTION_ON) {
+    if (s_config.domain[ESP_PD_DOMAIN_CNNT].pd_option != ESP_PD_OPTION_ON && top_domain_pd_allowed()) {
         pd_flags |= PMU_SLEEP_PD_CNNT;
     }
 #endif
@@ -2481,6 +2477,13 @@ static uint32_t get_power_down_flags(void)
         }
     }
 #endif
+
+#if CONFIG_IDF_TARGET_ESP32C6
+    if (!(pd_flags & PMU_SLEEP_PD_TOP)) {
+        // TOP power domain depends on the RTC_PERIPH power domain on ESP32C6, RTC_PERIPH should only be disabled when the TOP domain is down.
+        pd_flags &= ~RTC_SLEEP_PD_RTC_PERIPH;
+    }
+#endif
     return pd_flags;
 }
 

components/esp_pm/test_apps/esp_pm/main/CMakeLists.txt

@@ -5,5 +5,5 @@ set(sources "test_app_main.c"
 # the component must be registered as a WHOLE_ARCHIVE
 idf_component_register(SRCS ${sources}
                        INCLUDE_DIRS "."
-                       PRIV_REQUIRES unity esp_pm ulp driver esp_timer esp_psram
+                       PRIV_REQUIRES unity esp_pm ulp driver esp_timer esp_psram esp_vfs_console
                        WHOLE_ARCHIVE)

components/esp_pm/test_apps/esp_pm/main/test_pm.c

@@ -1,12 +1,13 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Unlicense OR CC0-1.0
  */
 
 #include <stdio.h>
 #include <stdlib.h>
 #include <stdint.h>
+#include <unistd.h>
 #include <time.h>
 #include <sys/time.h>
 #include <sys/param.h>
@@ -397,6 +398,29 @@ TEST_CASE("esp_timer with SKIP_UNHANDLED_EVENTS does not wake up CPU from sleep"
     TEST_ESP_OK(esp_timer_delete(periodic_timer));
 }
 
+TEST_CASE("Test USJ printing doesn't block CPU on chip wake-up", "[pm]")
+{
+    light_sleep_enable();
+    fflush(stdout);
+    fsync(fileno(stdout));
+    int64_t printing_time_cost_us = 0, time_end, time_start;
+
+    for (int i = 0; i < 20; ++i)
+    {
+        time_start = esp_timer_get_time();
+        printf("Dummy print %02d\n", i);
+        fflush(stdout);
+        fsync(fileno(stdout));
+        time_end = esp_timer_get_time();
+        printing_time_cost_us += time_end - time_start;
+        vTaskDelay(10);
+    }
+    int32_t avg_cost = (int32_t)(printing_time_cost_us / 20);
+    printf("Average cost per print %ld\n", avg_cost);
+    TEST_ASSERT_LESS_THAN(5000, avg_cost);
+    light_sleep_disable();
+}
+
 #endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE
 
 #endif // CONFIG_PM_ENABLE

components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld

@@ -157,7 +157,7 @@ systimer_hal_set_tick_rate_ops = 0x40002eac;
 /* Functions */
 sta_reset_beacon_timeout = 0x40003024;
 ieee80211_post_hmac_tx = 0x40003028;
-sta_rx_eapol = 0x4000302c;
+//sta_rx_eapol = 0x4000302c;
 /* Data (.data, .bss, .rodata) */
 len_dh_ie_ptr = 0x3fcdfa6c;
 g_authmode_threshold_failure_ptr = 0x3fcdfa68;

components/esp_system/port/soc/esp32c5/clk.c

@@ -189,6 +189,15 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
             rtc_clk_32k_enable(false);
             rtc_clk_32k_disable_external();
         }
+        // We have enabled all LP clock power in pmu_init, re-initialize the LP clock power based on the slow clock source after selection.
+        pmu_lp_power_t lp_clk_power = {
+            .xpd_xtal32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) || (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW),
+            .xpd_rc32k = 0,
+            .xpd_fosc = 1,
+            .pd_osc = 0
+        };
+        pmu_ll_lp_set_clk_power(&PMU, PMU_MODE_LP_ACTIVE, lp_clk_power.val);
+
         if (SLOW_CLK_CAL_CYCLES > 0) {
             /* TODO: 32k XTAL oscillator has some frequency drift at startup.
              * Improve calibration routine to wait until the frequency is stable.

components/esp_system/port/soc/esp32c6/clk.c

@@ -199,6 +199,14 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
         if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) {
             rtc_clk_rc32k_enable(false);
         }
+        // We have enabled all LP clock power in pmu_init, re-initialize the LP clock power based on the slow clock source after selection.
+        pmu_lp_power_t lp_clk_power = {
+            .xpd_xtal32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) || (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW),
+            .xpd_rc32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K),
+            .xpd_fosc = 1,
+            .pd_osc = 0
+        };
+        pmu_ll_lp_set_clk_power(&PMU, PMU_MODE_LP_ACTIVE, lp_clk_power.val);
 
         if (SLOW_CLK_CAL_CYCLES > 0) {
             /* TODO: 32k XTAL oscillator has some frequency drift at startup.

components/esp_system/port/soc/esp32c61/clk.c

@@ -167,6 +167,15 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
             rtc_clk_32k_enable(false);
             rtc_clk_32k_disable_external();
         }
+        // We have enabled all LP clock power in pmu_init, re-initialize the LP clock power based on the slow clock source after selection.
+        pmu_lp_power_t lp_clk_power = {
+            .xpd_xtal32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) || (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW),
+            .xpd_rc32k = 0,
+            .xpd_fosc = 1,
+            .pd_osc = 0
+        };
+        pmu_ll_lp_set_clk_power(&PMU, PMU_MODE_LP_ACTIVE, lp_clk_power.val);
+
         if (SLOW_CLK_CAL_CYCLES > 0) {
             /* TODO: 32k XTAL oscillator has some frequency drift at startup.
              * Improve calibration routine to wait until the frequency is stable.

components/esp_system/port/soc/esp32h2/clk.c

@@ -200,6 +200,14 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
         if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) {
             rtc_clk_rc32k_enable(false);
         }
+        // We have enabled all LP clock power in pmu_init, re-initialize the LP clock power based on the slow clock source after selection.
+        pmu_lp_power_t lp_clk_power = {
+            .xpd_xtal32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) || (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW),
+            .xpd_rc32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K),
+            .xpd_fosc = 1,
+            .pd_osc = 0
+        };
+        pmu_ll_lp_set_clk_power(&PMU, PMU_MODE_LP_ACTIVE, lp_clk_power.val);
 
         if (SLOW_CLK_CAL_CYCLES > 0) {
             /* TODO: 32k XTAL oscillator has some frequency drift at startup.

components/esp_system/port/soc/esp32p4/clk.c

@@ -161,6 +161,14 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
         if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) {
             rtc_clk_rc32k_enable(false);
         }
+        // We have enabled all LP clock power in pmu_init, re-initialize the LP clock power based on the slow clock source after selection.
+        pmu_lp_power_t lp_clk_power = {
+            .xpd_xtal32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K),
+            .xpd_rc32k = (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K),
+            .xpd_fosc = 1,
+            .pd_osc = 0
+        };
+        pmu_ll_lp_set_clk_power(&PMU, PMU_MODE_LP_ACTIVE, lp_clk_power.val);
 
         if (SLOW_CLK_CAL_CYCLES > 0) {
             /* TODO: 32k XTAL oscillator has some frequency drift at startup.

components/esp_wifi/test_apps/wifi_connect/pytest_wifi_connect.py

@@ -7,14 +7,14 @@
 @pytest.mark.esp32
 @pytest.mark.esp32c3
 @pytest.mark.esp32s3
-@pytest.mark.wifi_two_dut
+@pytest.mark.two_duts
 @pytest.mark.parametrize('count', [2], indirect=True)
 def test_wifi_connect_cases(case_tester: CaseTester) -> None:  # type: ignore
     case_tester.run_all_cases()
 
 
 @pytest.mark.esp32c2
-@pytest.mark.wifi_two_dut
+@pytest.mark.two_duts
 @pytest.mark.xtal_26mhz
 @pytest.mark.parametrize(
     'count, config, baud',
@@ -28,7 +28,7 @@ def test_wifi_connect_cases_esp32c2_xtal26m(case_tester: CaseTester) -> None:
 
 
 @pytest.mark.esp32c2eco4
-@pytest.mark.wifi_two_dut
+@pytest.mark.two_duts
 @pytest.mark.xtal_26mhz
 @pytest.mark.parametrize(
     'count, config, target, baud',
@@ -41,7 +41,7 @@ def test_wifi_connect_cases_esp32c2eco4_xtal26m(case_tester: CaseTester) -> None
     case_tester.run_all_cases()
 
 
-@pytest.mark.wifi_two_dut
+@pytest.mark.two_duts
 @pytest.mark.esp32c3eco7
 @pytest.mark.parametrize(
     'count, config, target',