Release/v5.5 #298
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Release/v5.5 #298
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(cherry picked from commit 9bfd9c5) Co-authored-by: zhanghaipeng <[email protected]>
(cherry picked from commit 2dcbd64) Co-authored-by: zhanghaipeng <[email protected]>
…spatch - Reference: https://nvd.nist.gov/vuln/detail/CVE-2020-0022 (cherry picked from commit 1f7fd91) Co-authored-by: zhanghaipeng <[email protected]>
…n attp_build_value_cmd - Reference: https://source.android.com/docs/security/bulletin/2024-03-01?hl=zh-cn (cherry picked from commit e1d39f6) Co-authored-by: zhanghaipeng <[email protected]>
- add length check in hci_hal_h4_hdl_rx_packet to prevent OOB - add adv data length check in btm_ble_cache_adv_data - add indicate data length check in BTA_GATTS_HandleValueIndication - add report length check in bta_hh_parse_keybd_rpt - add report length check in BTA_HdSendReport - add descriptor length check in BTA_HdRegisterApp - prevent buffer overflow in attribute processing (cherry picked from commit 71efec7) Co-authored-by: zhanghaipeng <[email protected]>
(cherry picked from commit 7e87624) Co-authored-by: zhanghaipeng <[email protected]>
(cherry picked from commit 24e023e) Co-authored-by: zhanghaipeng <[email protected]>
(cherry picked from commit e26b600) Co-authored-by: zhanghaipeng <[email protected]>
(cherry picked from commit b6b3b81) Co-authored-by: zhanghaipeng <[email protected]>
(cherry picked from commit 773814c) Co-authored-by: zhanghaipeng <[email protected]>
(cherry picked from commit 8b5dd75) Co-authored-by: zhanghaipeng <[email protected]>
(cherry picked from commit 8e0f74a) Co-authored-by: zhanghaipeng <[email protected]>
…ving_list (cherry picked from commit 4b44d8e) Co-authored-by: zhanghaipeng <[email protected]>
(cherry picked from commit b71c515) Co-authored-by: zhanghaipeng <[email protected]>
(cherry picked from commit a6730c7) Co-authored-by: zhanghaipeng <[email protected]>
(cherry picked from commit e741f09) Co-authored-by: zhanghaipeng <[email protected]>
…set_terminated_evt (cherry picked from commit d2baf3b) Co-authored-by: zhanghaipeng <[email protected]>
(cherry picked from commit b03ff3c) Co-authored-by: zhanghaipeng <[email protected]>
(cherry picked from commit 1ed5a44) Co-authored-by: zhanghaipeng <[email protected]>
(cherry picked from commit b163685) Co-authored-by: zhanghaipeng <[email protected]>
(cherry picked from commit f502b2a) Co-authored-by: zhanghaipeng <[email protected]>
* esp-openthread: thread_zigbee/esp-openthread@4a650cc2f * openthread: espressif/openthread@36b14d3ef * esp-idf: 871ec2c1e
… when PSRAM is enabled
… for encrypted writes This commit implements a workaround that allows ESP32-C5 to run at 240MHz CPU frequency normally, while automatically reducing CPU frequency during encrypted flash writes to ensure correct operation. The frequency limit is chip revision dependent: - v1.2 and above: limited to 160MHz during encrypted writes - v1.0 and below: limited to 80MHz during encrypted writes Key implementation details: - Frequency limiting is triggered automatically when esp_flash_write_encrypted() is called - Uses start() flags (ESP_FLASH_START_FLAG_LIMIT_CPU_FREQ) to integrate with OS layer - Works with both PM enabled and disabled configurations - Frequency is automatically restored after encrypted write completes - For ESP32-C5 with 120MHz flash, Flash clock and timing registers are adjusted when CPU frequency is reduced to 80MHz - SPI1 timing registers are configured during frequency switching since encrypted writes use SPI1 and must work correctly at reduced CPU frequencies Code improvements: - Use SOC_MSPI_FREQ_AXI_CONSTRAINED capability macro instead of hardcoded chip checks - Control workaround via Kconfig (CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED) instead of hardcoded macros - Add comprehensive test cases covering various PM configurations and edge cases This workaround enables ESP32-C5 applications to benefit from 240MHz CPU performance while maintaining reliable encrypted flash write functionality.
…ash encryption" This reverts commit 3c5d2e6.
- Fixed BLE assert lld_con.c 1479 (cherry picked from commit 2264124) Co-authored-by: chenjianhua <[email protected]>
…e/v5.5' fix(spi_flash): Add CPU frequency switching during flash encrypted write (v5.5) See merge request espressif/esp-idf!44305
Fixed BLE assert lld_con.c 1479 on ESP32-C3 and ESP32-S3(5106725) (v5.5) See merge request espressif/esp-idf!44328
…elease/v5.5' fix(coex): fix esp32 coex crash issue v5.5 See merge request espressif/esp-idf!44288
fix(nimble): Add change to cancel sync in case of reattempt (v5.5) See merge request espressif/esp-idf!43949
…v5.5' Fix potential CVE-2024-0039 out-of-bounds write in attp_build_value_cmd (v5.5) See merge request espressif/esp-idf!43807
…'release/v5.5' fix(ble/bluedroid): Fixed the issue that extend advertising might not restart if the connection fails (v5.5) See merge request espressif/esp-idf!44251
fix(ble/bluedroid): Fixed BLE incorrect device record count issue (v5.5) See merge request espressif/esp-idf!43597
fix(phy): fix esp32s2 phy lib issue v55 See merge request espressif/esp-idf!44341
…ase/v5.5' feat(parlio): support parlio gdma eof on p4 rev3.0 (v5.5) See merge request espressif/esp-idf!44038
fix(gdma): fix set dma burst size failure on p4 v3.0 (v5.5) See merge request espressif/esp-idf!44461
…yption This reverts commit 7145fc9.
chor(mcpwm): replace p4 psram test (v5.5) See merge request espressif/esp-idf!43682
…ode_v5.5' into 'release/v5.5' fix(wifi): fixed the crash issue when send espnow data in HE phymode (v5.5) See merge request espressif/esp-idf!44501
…e/v5.5' fix(esp_hw_support): fix RNG to LP Peri domain dependency on C5 (v5.5) See merge request espressif/esp-idf!44490
…e/v5.5' fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption (v5.5) See merge request espressif/esp-idf!44500
Update version to 5.5.2 See merge request espressif/esp-idf!44553
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