sysinfo: build cache-size on x86 only

Signed-off-by: kennytm <[email protected]>

Cargo.toml

@@ -19,6 +19,8 @@ doc-comment = "0.3"
 walkdir = "2.2.9"
 pnet_datalink = "0.23.0"
 num_cpus = "1.11.1"
+
+[target.'cfg(any(target_arch = "x86", target_arch = "x86_64"))'.dependencies]
 cache-size = "0.4.0"
 
 [target.'cfg(windows)'.dependencies]

src/sysinfo.rs

@@ -79,9 +79,25 @@ cfg_if! {
     }
 }
 
+#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
 pub extern crate cache_size;
 pub extern crate pnet_datalink as datalink;
 
+// Workaround https://github.com/lovesegfault/cache-size/issues/3. To be removed once cache-size can
+// be built outside of x86.
+#[cfg(not(any(target_arch = "x86", target_arch = "x86_64")))]
+pub mod cache_size {
+    pub fn l1_cache_size() -> Option<usize> {
+        None
+    }
+    pub fn l2_cache_size() -> Option<usize> {
+        None
+    }
+    pub fn l3_cache_size() -> Option<usize> {
+        None
+    }
+}
+
 pub use common::{AsU32, Pid, RefreshKind};
 pub use io::IOLoad;
 pub use net::NICLoad;
@@ -268,6 +284,7 @@ mod test {
     }
 
     #[test]
+    #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
     fn test_cache_size() {
         let caches = vec![
             ("l1-cache-size", ::cache_size::l1_cache_size()),