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Delay flush by one cycle #7

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Delay flush by one cycle

Delay flush by one cycle #7

Triggered via pull request November 26, 2024 12:01
@tilktilk
synchronize #2
delay_flush
Status Success
Total duration 16m 37s
Artifacts 1

main.yml

on: pull_request
Synthesize full core
37s
Synthesize full core
Build regression tests (riscv-tests)
45s
Build regression tests (riscv-tests)
Build regression tests (riscv-arch-test)
34s
Build regression tests (riscv-arch-test)
Run unit tests
5m 31s
Run unit tests
Check code formatting and typing
31s
Check code formatting and typing
Run regression tests (riscv-tests)
5m 58s
Run regression tests (riscv-tests)
Run regression tests (riscv-arch-test)
15m 41s
Run regression tests (riscv-arch-test)
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Artifacts

Produced during runtime
Name Size
verilog-full-core
537 KB