[pull] master from YosysHQ:master #258

And also fix the clock router to allow (with a warning) non-dedicated routing in case of false detection of clock wires. Signed-off-by: YRabbit <[email protected]>

- OSER4 can be located in neighboring IOs; - PLLVR also needs to rename the inputs. Signed-off-by: YRabbit <[email protected]>

Signed-off-by: YRabbit <[email protected]>

OSER16/IDES16 placement issue reports now indicate which location is having trouble. Signed-off-by: YRabbit <[email protected]>

In these chips, the midline IOs are still simple, but are no longer just IOBUF - that is, unlike the GW1N-1 IBUF and OBUF are not obtained by applying a signal to the OEN input. Signed-off-by: YRabbit <[email protected]>

Signed-off-by: YRabbit <[email protected]>

Using extra cell functions to mark disabled units using the PLL example. Signed-off-by: YRabbit <[email protected]>

Install the Himbaechel gowin chipdb .bin files to /usr/local/nextpnr/himbaehel/gowin Signed-off-by: YRabbit <[email protected]>

Signed-off-by: YRabbit <[email protected]>

Slightly change the Gowin device selection mechanism for database generation. By default, nothing is generated as before. Signed-off-by: YRabbit <[email protected]>

Signed-off-by: gatecat <[email protected]>

This option can be empty, in which case the virtualenv is left exactly as it was in the build environment.

Signed-off-by: gatecat <[email protected]>

Now the clock router can place a buffer into the specified network, which divides the network into two parts: from the source to the buffer, routing occurs through any available PIPs, and after the buffer to the sink, only through a dedicated global clock network. This is made specifically for the Tangnano20k where the external oscillator is soldered to a regular non-clock pin. But it can be used for other purposes, you just need to remember that the recipient must be a CLK input or output pin. The port/network to set the buffer to is specified in the .CST file: CLOCK_LOC "name" BUFG; Signed-off-by: YRabbit <[email protected]>

Signed-off-by: YRabbit <[email protected]>

Signed-off-by: gatecat <[email protected]>

We add support right here so that later I don’t have to make patches to the ports. Signed-off-by: YRabbit <[email protected]>

Signed-off-by: YRabbit <[email protected]>

Use himbaechel/gowin instead of himbaechel/gowin/gowin. Signed-off-by: YRabbit <[email protected]>

For GW2A-18 and GW1N-9 you need to specify the family in addition to partno. Signed-off-by: YRabbit <[email protected]>

Router 2 expects "update_route_delays" to be the first argument to `tmg.run`.

Signed-off-by: gatecat <[email protected]>

Fixed incorrect use of attributes instead of parameters. Signed-off-by: YRabbit <[email protected]>

…onnected Currently a segfault happens when the DI port is not specified. Leaving it unconnected is probably incorrect, but it shouldn't crash the placer. Fix by adding a check.

Signed-off-by: gatecat <[email protected]>

Signed-off-by: Balint Cristian <[email protected]>

Signed-off-by: gatecat <[email protected]>

Only pROM/pROMX9 for now Signed-off-by: YRabbit <[email protected]>

The following primitives are implemented for the GW1NZ-1 chip: * pROM - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32). * pROMX9 - read only memory - (bitwidth: 9, 18, 36). * SDPB - semidual port - (bitwidth: 1, 2, 4, 8, 16, 32). * SDPX9B - semidual port - (bitwidth: 9, 18, 36). * DPB - dual port - (bitwidth: 16). * DPX9B - dual port - (bitwidth: 18). * SP - single port - (bitwidth: 1, 2, 4, 8, 16, 32). * SPX9 - single port - (bitwidth: 9, 18, 36). Also: - The creation of databases for GW1NS-2 has been removed - this was not planned to be supported in Himbaechel from the very beginning and even examples were not created in apicula for this chip due to the lack of boards with it on sale. - It is temporarily prohibited to connect DFFs and LUTs into clusters because for some reason this prevents the creation of images on lower chips (placer cannot find the placement), although without these clusters the images are quite working. Requires further research. - Added creation of ALU with mode 0 - addition. Such an element is not generated by Yosys, but it is a favorite vendor element and its support here greatly simplifies the compilation of vendor netlists. Signed-off-by: YRabbit <[email protected]>

The following primitives are implemented for the GW1N-1, GW2A-18, GW2AR-18C, GW1NSR-4C, GW1NR-9C, GW1NR-9 and GW1N-4 chips: * pROM - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32). * pROMX9 - read only memory - (bitwidth: 9, 18, 36). * SDPB - semidual port - (bitwidth: 1, 2, 4, 8, 16, 32). * SDPX9B - semidual port - (bitwidth: 9, 18, 36). * DPB - dual port - (bitwidth: 16). * DPX9B - dual port - (bitwidth: 18). * SP - single port - (bitwidth: 1, 2, 4, 8, 16, 32). * SPX9 - single port - (bitwidth: 9, 18, 36). For GW1NSR-4C and GW1NR-9 chips, SP/SPX9 primitives with data widths of 32/36 bits are implemented using a pair of 16-bit wide primitives. Signed-off-by: YRabbit <[email protected]>

Signed-off-by: gatecat <[email protected]>

…ome of the headers

…he headers

…headers

…) and fixed an accidental copy problem

… and fixed an accidental copy problem

…memcpy()'ing into a non-POD type from the compiler There is still the possibility that this can explode horribly, but the result should be the same codegen and fixes the warning This also makes the helpers `inline` so they'll usually be compiled out for a nice speed boost

Signed-off-by: gatecat <[email protected]>

The OCE signal in the SP(X)9B primitive is intended to control the built-in output register. The documentation states that this port is invalid when READ_MODE=0 is used. However, it has been experimentally established that you cannot simply apply VCC or GND to it and forget it - the discrepancy between the signal on this port and the signal on the CE port leads to both skipping data reading and unnecessary reading after CE has switched to 0. Here we force these ports to be connected to the network, except in the case where the user controls the OCE signal using non-constant signals. Also: * All PIPs for clock spines are made inaccessible to the common router - in general, using these routes for signals that have not been processed by a special globals router is fraught with effects that are difficult to detect. * The INV primitive has been added purely to speed up development - this primitive is not generated by Yosys, but is almost always present in vendor output files. Signed-off-by: YRabbit <[email protected]>

Signed-off-by: YRabbit <[email protected]>

Signed-off-by: gatecat <[email protected]>

This type setting is not needed here - the packer distinguishes memory features by the X9 attribute, which will be correct anyway. Signed-off-by: YRabbit <[email protected]>

Ignore networks without users. Signed-off-by: YRabbit <[email protected]>

* Don't stop at the first bad "arc", but use the global network to the maximum. * Report partial/full use of global wires for the network. * In case of complete routing failure, releasing the source - this is actually a BUGFIX. Signed-off-by: YRabbit <[email protected]>

Signed-off-by: YRabbit <[email protected]>

Semi-dual port BSRAM (in Gowin terminology) has the same feature as Single Port - the CE and OCE signals must be synchronized. Such a sin has not yet been noticed for Dual Port. Signed-off-by: YRabbit <[email protected]>

Signed-off-by: gatecat <[email protected]>

A small improvement - do not waste time analyzing already processed networks in the previous step (and possibly steps). Signed-off-by: YRabbit <[email protected]>

Corrects the situation when it is impossible to use IOBUF with two IOLOGIC elements at the same time - input and output. Addresses #1275 This is done by dividing one IOLOGIC Bel into two - input IOLOGIC and output IOLOGIC plus checking for compatibility of the cells located there. At the moment, this check is simple and allows only the combination of DDR and DDRC primitives. Signed-off-by: YRabbit <[email protected]>

Signed-off-by: YRabbit <[email protected]>

For the following primitives: - PADD9 - PADD18 - MULT9X9 - MULT18X18 - MULT36X36 - MULTALU18X18 - MULTALU36X18 - MULTADDALU18X18 - ALU54D packing and processing of fixed wires between macro and between DSP blocks is implemented. Clusters of DSP and macro blocks are processed using custom placement of cluster elements. Signed-off-by: YRabbit <[email protected]>

Signed-off-by: YRabbit <[email protected]>

…d use it. Resolves issue #1298.

If the CLKIN input of the PLL is connected to a special pin, then it makes sense to try to place the PLL so that it uses a direct implicit non-switched connection to this pin. The transfer of information about pins for various purposes has been implemented (clock input signal, feedback, etc), but so far only CLKIN is used. Signed-off-by: YRabbit <[email protected]>

Do not search for pads if the signal source for the PLL is something other than the IO pin - these are guaranteed to already be placed and have a bound Bel. Signed-off-by: YRabbit <[email protected]>

When multiplying 36 bits by 36 bits using four 18x18 multipliers, the sign bits of the higher 18-bit parts of the multipliers were correctly switched, but what was incorrect was leaving the sign bits of the lower parts of the multipliers uninitialized. They now connect to VSS. Addresses YosysHQ/apicula#242 Signed-off-by: YRabbit <[email protected]>

Signed-off-by: gatecat <[email protected]>

Co-authored-by: Lofty <[email protected]> Signed-off-by: gatecat <[email protected]>

Signed-off-by: gatecat <[email protected]>

Add description of BSRAM harness In some cases, Gowin IDE adds a number of LUTs and DFFs to the BSRAM. Here we are trying to add similar elements. More details with pictures: https://github.com/YosysHQ/apicula/blob/master/doc/bsram-fix.md Signed-off-by: YRabbit <[email protected]>

It seems that the internal registers on the BSRAM output pins in READ_MODE=1'b1 (pipeline) mode do not function properly because in the images generated by Gowin IDE an external register is added to each pin, and the BSRAM itself switches to READ_MODE=1'b0 (bypass) mode . This is observed on Tangnano9k and Tangnano20k boards. Here we repeat this fix. Signed-off-by: YRabbit <[email protected]>

In the images generated by Gowin IDE, the signals for dynamic BSRAM block selection (BLKSEL[2:0]) are not always connected directly to the ports - some chips add LUT2, LUT3 or LUT4 to turn these signals into Clock Enable. Apparently there are chips with an error in the operation of these ports. Here we make such a decoder instead of using ports directly. Signed-off-by: YRabbit <[email protected]>

As the board on the GW1N-1 chip becomes a rarity, its replacement is the Tangnano1k board with the GW1NZ-1 chip. This chip has a unique mechanism for turning off power to important things such as OSC, PLL, etc. Here we introduce a primitive that allows energy saving to be controlled dynamically. We also bring the names of some functions to uniformity. Signed-off-by: YRabbit <[email protected]>

For pROM(X9) primitives in images generated by Gowin IDE, there is an interesting recommunication of inputs depending on the data bit depth. For example, in some cases, a high logical level may be applied to the Write Enable input, which, let’s say, is not entirely usual for Read Only memory. Here we will do similar manipulations. In addition, several minor bug fixes are included: - Fixed bit numbering for non-X9 series primitives. - Fixed decoder generation for BLKSEL - do not assume unused inputs are connected to GND. - Use default values for BSRAM parameters - don't assume their mandatory presence. Signed-off-by: YRabbit <[email protected]>

The statement in the Gowin documentation that in the reading mode "READ_MODE=0" the output register is not used and the OCE signal is ignored is not confirmed by practice - if the OCE was left unconnected or connected to the constant network, then a change in output data was observed even with CE=0, as well as the absence of such at CE=1. Synchronizing CE and OCE helps and the memory works properly in complex systems such as RISC-V emulation and i8080 emulation (with 32K RAM and 16K BSRAM based ROM), but there is no theoretical basis for this fix, so it is a hack. Signed-off-by: YRabbit <[email protected]>

It was not taken into account that there are only 6 ALUs per cell. As a result, on complex designs where ALUs and LUT-based memory are involved and there are many LUTs (like in the RISCV emulator), there were sometimes false positives about placement conflicts. Signed-off-by: YRabbit <[email protected]>

DQCE and DCS primitives are added. DQCE allows the internal logic to enable or disable the clock network in the quadrant. When clock network is disabled, all logic drivern by this clock is no longer toggled, thus reducing the total power consumtion of the device. DCS allows you to select one of four sources for two clock wires (6 and 7). Wires 6 and 7 have not been used up to this point. Since "hardware" primitives operate strictly in their own quadrants, user-specified primitives are converted into one or more "hardware" primitives as needed. Also: - minor edits to make the most of helper functions like connectPorts() - when creating bases, the corresponding constants are assigned to the VCC and GND wires, but for now huge nodes are used because, for an unknown reason, the constants mechanism makes large examples inoperable. So for now we remain on the nodes. Compatible with older Apicula databases. Signed-off-by: YRabbit <[email protected]>

We filter out PIPs from these chips that bypass DCS. Signed-off-by: YRabbit <[email protected]>

* Himbaechel Gowin: Add support for CLKDIV and CLKDIV2 * Himbaechel Gowin: Add support for CLKDIV and CLKDIV2 * Gowin Himbaechel: HCLK Bug fixes and corrections

* kernel: Add SDC file parser * kernel: Add sdc as valid option * kernel/sdc: Add error on EOF when fetching strings * kernel/sdc: WIP command parsing for set_false_path * kernel/sdc: Fully parse set_false_path * kernel/sdc: Handle review comments

Signed-off-by: YRabbit <[email protected]>

* Gowin. Implement the UserFlash primitive Some Gowin chips have embedded flash memory accessible from the fabric. Here we add primitives that allow access to this memory. Signed-off-by: YRabbit <[email protected]> * Gowin. Fix cell creation Signed-off-by: YRabbit <[email protected]> --------- Signed-off-by: YRabbit <[email protected]>

Some Clocks PIPS were not created due to a check for the presence of a delay class, now all wires are attributed to the class so that there is no longer any need for this check. Signed-off-by: YRabbit <[email protected]>

* Gowin. Add DHCEN primitive. This primitive allows you to dynamically turn off and turn on the networks of high-speed clocks. This is done tracking the routes to the sinks and if the route passes through a special HCLK MUX (this may be the input MUX or the output MUX, as well as the interbank MUX), then the control signal of this MUX is used. Signed-off-by: YRabbit <[email protected]> * Gowin. Change the DHCEN binding Use the entire PIP instead of a wire - avoids normalisation and may also be useful in the future when calculating clock stuff. Signed-off-by: YRabbit <[email protected]> --------- Signed-off-by: YRabbit <[email protected]>

* Gowin. Implement the EMCU primitive. Add support for the GW1NSR-4C's embedded Cortex-M3 processor. Since it uses flash in its own way, we disable additional flash processing for this case. Signed-off-by: YRabbit <[email protected]> * Gowin. Fix merge. Signed-off-by: YRabbit <[email protected]> --------- Signed-off-by: YRabbit <[email protected]>

* Fix truncation of output seed value from 64 bits to 32 bits (int instead of uint64) when written to json file. * Fix input seed value conversion when --seed option is used. * Remove input seed value scrambling (use of rngseed()) when --seed or --randomize-seed option is used since the output seed value will be the scrambled value and not the seed that was actually supplied or generated.

Signed-off-by: gatecat <[email protected]>

timing: Add clock2clock delay as seperate timing line item.

timing_log: Use common segment type strings

timing: Fix max_delay_by_domain_pair function timing: Fix hold time check

timing: Disable clock_skew analysis by default

…ipped

…s and share identification code

Signed-off-by: gatecat <[email protected]>

… XDC file

…DC commands

…r better interoperability with other synthesis tools and RTL languages

* Gowin. Fix the port check for connectivity. What happens is that it's not enough to check for a network, we also need to make sure that the network is functional: has src and sinks. And the style edits - they get automatically when I make sure to run clang-format10. Signed-off-by: YRabbit <[email protected]> * Gowin. Fix the port check for connectivity. What happens is that it's not enough to check for a network, we also need to make sure that the network is functional: has src and sinks Signed-off-by: YRabbit <[email protected]> --------- Signed-off-by: YRabbit <[email protected]>

Signed-off-by: gatecat <[email protected]>

…1381)

* apicula: add support for magic sip pins * fix nullptr check * DDR fix by xiwang * WIP support for setting the iostd * add iostd

Signed-off-by: gatecat <[email protected]>

* Gowin. FFs placement. * Allow clusters to be created from FFs and LUTs; * Immediately create pass-through LUTs from free LUTs adjacent to FF - at the same time ensure alternating use of LUT inputs; * In case of constant networks, such pass-through LUTs are disconnected from networks altogether; * Allow FF to be placed directly into SSRAM slides - this is useful when using synchronous reading. Signed-off-by: YRabbit <[email protected]> * Gowin. Fix aux name creation Signed-off-by: YRabbit <[email protected]> * Gowin. Use I3 for pass-trough LUTs Signed-off-by: YRabbit <[email protected]> --------- Signed-off-by: YRabbit <[email protected]>

* Extend Himbaechel API with gfx drawing methods * Add bel drawing in example uarch * changed API and added tile wire id in db * extend API so we can distinguish CLK wires * added bit more wires * less horrid way of handling gfx ids * loop wire range * removed not needed brackets * bump database version to 5 * Removed not used GfxFlags

Commits on Oct 9, 2023

compile fix

mmicko committed Oct 9, 2023

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readme: update build prerequisites

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Placer: Fix static legalise radius (#1382 )

meiniKi authored Oct 8, 2024

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[pull] master from YosysHQ:master #258

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