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Welcome to the UPduino-v3.0 wiki!

Here is a proposed set of features for the UPduino 3.0 design:

Requirements

Identical pinout as UPduino 2.0/2.1
Same cost as current UPduino ($19.95)
Switch to KiCAD: Current design is done in Eagle. Eagle is free only for non-commercial projects and then too only for 2 layer boards. KiCAD is an OSHW friendly tool in contrast with no such limitations.
0.1" header format
Better layout
Oscillator option

Board layout:
- 4 layer board, solid ground plane, dedicated power layer for 3.3V and 1.2V distribution
- Any optional bridges must be done using special bridge-type footprint instead of resistors to make modification easy
- All passives to be no smaller than 0603 footprint
- Fix silkscreen so its easy to read, add Pb Free, WEEE symbol, "Made in USA"
- Move Micro USB connector inboard a little bit to allow clean depanelization
Power
- Dedicated power and ground planes
- Minimum of 10uF bulk capacitance on all power rails: USB, 3.3V, 1.2V
- Dedicated decoupling capacitance on each FPGA pin placed close the FPGA pin
- Power decoupling per FTDI recommendations (using ferrite beads)
- Change LDO's to be smaller parts, capable of 200mA max output
Oscillator:
- 12MHz crystal oscillator to replace the resonator for stability
- Solder bridge option to connect the 12MHz oscillator to the FPGA
Flash
- qSPI option using the currently unused pin 10, 20 (layout permitting)
- DTR capable flash to support even higher throughput
Programming:
- Connect DONE signal to the FTDI
- FPGA CRAM programming capability
LED:
- Smaller 3 color LED?
- Bring out the 3 color LED pins to alternate (DNI) LED footprints to allow these to be used for other applications such as IR LED's etc.
Sample code:
- Ship with RISCV port instead of very simple blinky