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The project involves designing a Simple RISC Computer (SRC) processor with 23 instructions, 32 registers, a control unit, data path, and memory components, aiming to create a functional CPU architecture capable of executing instructions.
🧠 Pipelined Processor is to design, implement and test a Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor.
This repository contains the CENG3010 Computer Organization course projects. The first project involves developing a GUI-based 32-bit MIPS simulator, while the second project centers on designing a custom 16-bit MIPS-like processor with a unique instruction set.
Software for 3-axis machine control. It uses a Raspberry Pi with motor controllers and additional electronics. Features: visualization, GPIO emulation, touchscreen capability, and Cython optimization. Tested on Windows(visu) and Raspberry Pi OS. Under development with Pyside2 and OpenGl.
A Datapath design which able to execute store operation as memory instruction, substraction and or operations as arithmetic instruction by Logisim. Additional explanations in readme.
Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.