Add spilOverJtag for Virtex6

[UweBonnes]

This is #307 reworked:

• Fix some problems when compiling the xilinx spiOverJtag files
• Refactor xilinx_spiOverJtag.v for better readability and extensability. At least all xilinx families compile.
• Add code for virtex6 in xilinx_spiOverJtag.v and some boards used here.

If you feel uneager about the verilog changes, can you perhaps drop the rework and only add the bitfile?

Cheers

[trabucayre]

Amazing works thanks!
I have to check more closely verilog modifications but seems good to me, this adds some duplicate portions but seems more clear.
I'm just a bit hesitant about wpn/holdn and for csn/sck on fgg484 package

[trabucayre]

LGTM.
But by adding t for some constraints its maybe required to update corresponding board and rename bitstreams?

[UweBonnes]

the t constraint is only added to one fpga file. And that bit file is added as a new file in the commit. So no need to recompile all xilinx bitfiles. But the compile also resulted in bitfiles not yet added. What to do with those?

[trabucayre]

True. I'm wrong. bitstream naming is unchanged so this as no impact on already supported board and bitstream.
Is a rebase is required? maybe for commit "spiOverJtag: Fix errors on xc6slx150tfgg484, but it's not really required. As you want

[UweBonnes]

I see no real need to rebase.

[trabucayre]

Applied. Thanks @UweBonnes