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@trabucayre trabucayre released this 19 Mar 09:38
· 672 commits to master since this release
v0.8.0
bbd7558

Evolution summary:

core:

new

  • part: add map manufacturer id <-> name
  • jtag: adding method to inject device into active device list
  • ftdi MPSSE / jtag: add option to use neg edge for TDO's sampling
  • xilinx: adding zynqmp support and a method to init this family of devices

update

  • jtag: better display for unknown IDCODE
  • jtag: improving jtag chain detection: now searching for masked and unmasked idcode
  • display: use a less dark blue
  • Nicer layout for the boards/fpga/cables table
  • main: bitstream default target depends on mode spi/jtag

fix

  • ftdiJtagMPSSE: fix read/write polarity: always write on neg, read is by default on pos but may on neg with arty
  • Darwin cmake config is missing Security framework
  • ftdiJtagMPSSE,ftdipp_mpsse: fix verbose level -> must be an int8_t not uint8_t
  • jtag: fix shiftIR: bypass_after must be computed in all case

cable

new

  • digilent jtag-smt2-nc
  • Olimex ARM-USB-OCD-H
  • SEGGER J-Link

board

new

  • alinx AXU2CGA
  • Xilinx AC701 development kit
  • Xilinx/TUL PYNQ-Z2
  • Xilinx Zynq-7000 SoC ZC702 Evaluation Kit
  • Xilinx Zynq-7000 SoC ZC706 Evaluation Kit
  • Xilinx ZynqMPSoC ZCU102 Evaluation Kit
  • CERN SPEC150
  • colorlight-i9
  • digilent genesys2
  • digilent zybo_z7 10/20
  • QMTech qmtechCycloneV_5cefa5f23 board
  • QMTech Kintex7 Core Board
  • sipeed tangnano1k
  • sipeed tangnano9k
  • Terasic DE1-SoC board

part

new

  • Xilinx Spartan6 xc6slx150T
  • Xilinx Kintex 160T
  • Xilinx Zynq XC7Z045
  • Xilinx ZynqMPSoC XCZU2CG
  • Xilinx ZynqMPSoC XCZU9EG
  • Gowin GW1NZ-1
  • Gowin GW1NR-9C
  • Altera CycloneV 5CEFA5
  • Altera CycloneV SoC 5CSEMA5

update

  • ice40: add CRAM support

fix

  • ice40: Add override specifier to resolve compiler warnings

spiFlash

new

  • Spansion S25FL256S
  • Spansion S25FL256L
  • Microchip SST26VF032B

update

  • spiFlash: add no block protect use case

fix

  • spiFlash: when no subsector_erase compute end_addr with correct block size
  • spiFlashdb: fix bp_offset list
  • spiFlash: force subsector only for SST26VF032B
  • spiFlash: fix overflow test (#172)

spiOverJtag

new

  • Xilinx spartan6 FTG 256 ucf
  • Xilinx spartan6 LX16 FTG256
  • Xilinx spartan6 LX16 CSG324
  • Xilinx Spartan6 LX150T
  • add spiOverJtag build process for Kintex7 ffg900-2 packages, amend and extend build process for ff676-1 package
  • Add spiOverJtag support for Xilinx xc7k325tffg676 part.
  • spiOverJtag/spiOverJtag_5cefa5f23.rbf.gz bitstream to write flash

update

  • compress the kintex7 bitstreams

CI

new

  • add CI for macOS
  • use reusable composite action and reusable workflow from msys2/setup-msys2

fix

  • fix msys2 build failure
  • fix step 'Show package content'

doc

new

  • FPGAs: ice40 memory support
  • cable: move to yml
  • declare board compatibility through a YAML file
  • declare FPGA compatibility list through YAML file
  • conf: add intersphinx mapping 'constraints'
  • cross-reference FPGA compatibility table and vendor notes
  • boards: iCE40UP5K-B-EVN
  • cable: RV-Debugger-BL702

update

  • board: add field 'Constraints'
  • install.rst
  • boards: iCE40-HX8K: memory ok

fix

  • debian command

Contributors

Contributors

rwhitby, pepijndevos, and 15 other contributors
Assets 9
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