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How to inject some Tcl code between synthesis and implementation stages for Vivado

Status: Open.

#903 In ucb-bar/hammer;

· m-kru opened on Mar 11, 2026

Handling multiple, scoped, optional constraint files

Status: Open.

#902 In ucb-bar/hammer;

· m-kru opened on Mar 9, 2026

Xcelium reported multiple "Unknown option *** "

bug

Status: Open.

#898 In ucb-bar/hammer;

· idwwwoqq808 opened on Oct 29, 2025

Is this project actively maintained?

Status: Open.

#895 In ucb-bar/hammer;

· osamimi opened on Sep 13, 2025

Adding action for Automatic Test Pattern Gneration (ATPG)

enhancement

Status: Open.

#894 In ucb-bar/hammer;

· franout opened on Sep 9, 2025

Add default empty value for lvs.icv.equiv_files key

bug

Status: Open.

#885 In ucb-bar/hammer;

· sunjin-choi opened on Feb 21, 2025

find_regs_paths.json not escape registers correctly, causing post-synthesis simulation to fail

bug

Status: Open.

#884 In ucb-bar/hammer;

· cedard234 opened on Feb 15, 2025

2 Problems about VLSI Flow

bug

Status: Open.

#874 In ucb-bar/hammer;

· exhaust-create opened on Aug 31, 2024

DC plugin doesn't work

Status: Open.

#860 In ucb-bar/hammer;

· exhaust-create opened on May 13, 2024

Option for additional command line arguments for tools

enhancement

Status: Open.

#786 In ucb-bar/hammer;

· krabo0om opened on May 9, 2023

ASAP7 "Foundry" SRAMs

enhancement

Status: Open.

#739 In ucb-bar/hammer;

· harrisonliew opened on Mar 13, 2023

VCS -top option is ambiguous

low priorityEasy workaround exists, regular QoL issueEasy workaround exists, regular QoL issue

SynopsysSpecific to a Synopsys toolSpecific to a Synopsys tool

Status: Open.

#771 In ucb-bar/hammer;

· harrisonliew opened on Feb 3, 2023