comment out layout codegen

codegen/src/lib.rs

@@ -151,12 +151,11 @@ pub fn derive_io(input: TokenStream) -> TokenStream {
     let parsed = parse_macro_input!(input as DeriveInput);
     let input = handle_error!(IoInputReceiver::from_derive_input(&parsed));
     let schematic = schematic_io(&input);
-    let layout = layout_io(&input);
+    // let layout = layout_io(&input);
     let io_core_impl = io_core_impl(&input, true);
     quote!(
         #io_core_impl
         #schematic
-        #layout
     )
     .into()
 }

substrate/src/layout/conv.rs

@@ -26,13 +26,13 @@ pub(crate) struct LayirLibExportContext<L> {
     conv: LayirLibConversion,
 }
 
-/// An SCIR library with associated conversion metadata.
+/// A LayIR library with associated conversion metadata.
 pub struct RawLib<L> {
-    /// The SCIR library.
+    /// The LayIR library.
     pub layir: layir::Library<L>,
     /// Associated conversion metadata.
     ///
-    /// Can be used to retrieve SCIR objects from their corresponding Substrate IDs.
+    /// Can be used to retrieve LayIR objects from their corresponding Substrate IDs.
     pub conv: LayirLibConversion,
 }
 
@@ -58,12 +58,12 @@ impl<L> LayirLibExportContext<L> {
 pub struct LayirExportError;
 
 impl<L: Clone> RawCell<L> {
-    /// Export this cell and all subcells as a SCIR library.
+    /// Export this cell and all subcells as a LayIR library.
     ///
-    /// Returns the SCIR library and metadata for converting between SCIR and Substrate formats.
+    /// Returns the LayIR library and metadata for converting between LayIR and Substrate formats.
     ///
-    /// Consider using [`export_multi_top_scir_lib`] if you need to export multiple cells
-    /// to the same SCIR library.
+    /// Consider using [`export_multi_top_layir_lib`] if you need to export multiple cells
+    /// to the same LayIR library.
     pub(crate) fn to_layir_lib(&self) -> Result<RawLib<L>, LayirExportError> {
         let mut lib_ctx = LayirLibExportContext::new();
 
@@ -73,7 +73,7 @@ impl<L: Clone> RawCell<L> {
         })
     }
 
-    /// Exports this [`RawCell`] to a SCIR cell if it has not already been exported. Should only be called
+    /// Exports this [`RawCell`] to a LayIR cell if it has not already been exported. Should only be called
     /// on top cells or un-flattened cells.
     fn to_layir_cell(
         &self,
@@ -121,11 +121,11 @@ impl<L: Clone> RawCell<L> {
     }
 }
 
-/// Export a collection of cells and all their subcells as a SCIR library.
+/// Export a collection of cells and all their subcells as a LayIR library.
 ///
-/// Returns the SCIR library and metadata for converting between SCIR and Substrate formats.
-/// The resulting SCIR library will **not** have a top cell set.
-/// If you want a SCIR library with a known top cell, consider using [`RawCell::to_scir_lib`] instead.
+/// Returns the LayIR library and metadata for converting between LayIR and Substrate formats.
+/// The resulting LayIR library will **not** have a top cell set.
+/// If you want a LayIR library with a known top cell, consider using [`RawCell::to_layir_lib`] instead.
 pub(crate) fn export_multi_top_layir_lib<L: Clone>(
     cells: &[&RawCell<L>],
 ) -> Result<RawLib<L>, LayirExportError> {

substrate/src/types/mod.rs

@@ -208,52 +208,52 @@ pub struct ArrayBundle<T: HasBundleKind> {
 
 // BEGIN COMMON IO TYPES
 
-// /// The interface to a standard 4-terminal MOSFET.
-// #[derive(Debug, Default, Clone, Io)]
-// pub struct MosIo {
-//     /// The drain.
-//     pub d: InOut<Signal>,
-//     /// The gate.
-//     pub g: Input<Signal>,
-//     /// The source.
-//     pub s: InOut<Signal>,
-//     /// The body.
-//     pub b: InOut<Signal>,
-// }
-//
-// /// The interface to which simulation testbenches should conform.
-// #[derive(Debug, Default, Clone, Io, PartialEq, Eq)]
-// pub struct TestbenchIo {
-//     /// The global ground net.
-//     pub vss: InOut<Signal>,
-// }
-//
-// /// The interface for 2-terminal blocks.
-// #[derive(Debug, Default, Clone, Io)]
-// pub struct TwoTerminalIo {
-//     /// The positive terminal.
-//     pub p: InOut<Signal>,
-//     /// The negative terminal.
-//     pub n: InOut<Signal>,
-// }
-//
-// /// The interface for VDD and VSS rails.
-// #[derive(Debug, Default, Clone, Io)]
-// pub struct PowerIo {
-//     /// The VDD rail.
-//     pub vdd: InOut<Signal>,
-//     /// The VSS rail.
-//     pub vss: InOut<Signal>,
-// }
-//
-// /// A pair of differential signals.
-// // TODO: Create proc macro for defining un-directioned (non-IO) bundle types directly.
-// #[derive(Debug, Default, Copy, Clone, Io)]
-// pub struct DiffPair {
-//     /// The positive signal.
-//     pub p: InOut<Signal>,
-//     /// The negative signal.
-//     pub n: InOut<Signal>,
-// }
+/// The interface to a standard 4-terminal MOSFET.
+#[derive(Debug, Default, Clone, Io)]
+pub struct MosIo {
+    /// The drain.
+    pub d: InOut<Signal>,
+    /// The gate.
+    pub g: Input<Signal>,
+    /// The source.
+    pub s: InOut<Signal>,
+    /// The body.
+    pub b: InOut<Signal>,
+}
+
+/// The interface to which simulation testbenches should conform.
+#[derive(Debug, Default, Clone, Io, PartialEq, Eq)]
+pub struct TestbenchIo {
+    /// The global ground net.
+    pub vss: InOut<Signal>,
+}
+
+/// The interface for 2-terminal blocks.
+#[derive(Debug, Default, Clone, Io)]
+pub struct TwoTerminalIo {
+    /// The positive terminal.
+    pub p: InOut<Signal>,
+    /// The negative terminal.
+    pub n: InOut<Signal>,
+}
+
+/// The interface for VDD and VSS rails.
+#[derive(Debug, Default, Clone, Io)]
+pub struct PowerIo {
+    /// The VDD rail.
+    pub vdd: InOut<Signal>,
+    /// The VSS rail.
+    pub vss: InOut<Signal>,
+}
+
+/// A pair of differential signals.
+// TODO: Create proc macro for defining un-directioned (non-IO) bundle types directly.
+#[derive(Debug, Default, Copy, Clone, Io)]
+pub struct DiffPair {
+    /// The positive signal.
+    pub p: InOut<Signal>,
+    /// The negative signal.
+    pub n: InOut<Signal>,
+}
 
 // END COMMON IO TYPES