D2D Dummy Loopback Module #49
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I can't reproduce the CI scalafmt failure locally, @ethanwu10 can you try to repro locally? |
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CI failure is a deprecation warning for Chisel Scala FIRRTL compiler; do we want to use it anyways, or use the CIRCT stage? |
| io.plStateStatus := PhyState.active // TODO: this is part of the FDI state machine | ||
| } | ||
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| object D2DDummyLoopbackMain extends App { |
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To suppress the SFC deprecation warning:
| object D2DDummyLoopbackMain extends App { | |
| @annotation.nowarn("cat=deprecation&origin=chisel3.stage.ChiselStage") | |
| object D2DDummyLoopbackMain extends App { |
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Thanks, we will just disable the warning. CirctStage is only a thing in Chisel 5+ and Chipyard will be stuck on Chisel 3.6 for a while. This is also not maintained anymore, so there's no point in using it (https://github.com/sifive/chisel-circt).
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circt.stage.CirctStage does exist (and works) in Chisel 3.6; using SFC is an option though to avoid non-Scala dependencies to elaborate.
| io.plStateStatus := PhyState.active // TODO: this is part of the FDI state machine | ||
| } | ||
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| object D2DDummyLoopbackMain extends App { |
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circt.stage.CirctStage does exist (and works) in Chisel 3.6; using SFC is an option though to avoid non-Scala dependencies to elaborate.
| @@ -81,6 +81,7 @@ class Fdi(params: FdiParams) extends Bundle { | |||
| * | |||
| * Encompasses `lp_dllp` and `lp_dllp_valid` from the UCIe specification. | |||
| */ | |||
| // TODO: we don't use dllp's at all, make these IOs optional | |||
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I think we should keep the IOs in the bundle even if we are never using them, and drive them with constants / add assertions instead; this way our IO is always spec-compliant.
| // LatencyPipe from rocket-chip | ||
| // https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/util/LatencyPipe.scala |
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We may want to vendor utils from rocket-chip in a dedicated package / directory (there are definitely more things we want to steal, e.g. AsyncQueue)
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| package edu.berkeley.cs.ucie.digital | |||
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I think this should go in the main build, in the interfaces package - it could conceivably be used by other consumers of this repo to test their own IP. We're putting other verification-related IP for FDI and RDI in the interfaces package as well.
Add an empty D2D module with the FDI Bundle that just loops back lp_data to pl_data through a latency pipe. Tie off unused outputs. Add a test to make sure it elaborates cleanly. Next steps (in future PRs) are 1) generate SystemVerilog collateral from reflecting over the FDI Bundle (interface, module wrapper, structs) and 2) creating simple VIP to drive lp_data and fetch pl_data (both in Scala and SystemVerilog, sharing transaction and agent hierarchies).