Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

CRC Generation Module #54

Open
wants to merge 32 commits into
base: main
Choose a base branch
from
Open
Show file tree
Hide file tree
Changes from 16 commits
Commits
Show all changes
32 commits
Select commit Hold shift + click to select a range
bf62871
Wrote initial module structure
ronitnag04 Oct 23, 2023
6a36944
Added Reset Logic
ronitnag04 Oct 23, 2023
472b6da
Generated CRC-16 Lookup table
ronitnag04 Oct 23, 2023
78584bc
Created lookup table class for CRC calculations
ronitnag04 Oct 23, 2023
d27e94b
Fixed lookup table format and successful import
ronitnag04 Oct 23, 2023
d2ab201
Set up CRC Gen algorithm (not functional)
ronitnag04 Oct 24, 2023
7341b9f
Updated CRCGenerator for Shift Register (non-functional)
ronitnag04 Oct 25, 2023
643b383
Compiled, functioning shift, algorithm incorrect
ronitnag04 Oct 26, 2023
2b9bb8a
Test Structure fixed
ronitnag04 Oct 26, 2023
a0ed001
Resolved issues, added test cases
ronitnag04 Oct 26, 2023
ad22060
Added test cases
ronitnag04 Oct 26, 2023
eaead7e
style: Refactored to snake_case, split test modules
ronitnag04 Oct 26, 2023
ba286e3
Refactored data_in to message Decoupled ReadyValid3IO
ronitnag04 Oct 26, 2023
6ee2f2b
Remove helper files
ronitnag04 Oct 26, 2023
63cd816
Format changes
ronitnag04 Nov 1, 2023
7a8e649
Format with scalafmtAll
ronitnag04 Nov 1, 2023
0b3c701
Added back-to-back 1024-bit test
ronitnag04 Nov 1, 2023
618df0b
Reconfigured CRC 3IO interface, documentation
ronitnag04 Nov 1, 2023
252ed7e
Fixed documentation typo
ronitnag04 Nov 1, 2023
b2837fd
Reconfigured IO, testing with DecoupledDriver
ronitnag04 Nov 2, 2023
966ba5e
Fixed lookup table docstring
ronitnag04 Nov 2, 2023
5465b45
Fixed with scalafmtAll
ronitnag04 Nov 2, 2023
2bf4ecb
refactor: make CRC16Lookup an object
ethanwu10 Nov 2, 2023
7f83684
Fixed error test case
ronitnag04 Nov 3, 2023
8946b69
Reconfigured CRC update to one line
ronitnag04 Nov 15, 2023
d6d3b53
Added paramterized bytes consumed per cycle
ronitnag04 Nov 18, 2023
97a8bb0
Merge branch 'main' into d2dadapter-crc
ronitnag04 Nov 18, 2023
cbeb474
Refactored to only send next-consumed message bits
ronitnag04 Nov 29, 2023
091cddf
Fixed formatting
ronitnag04 Nov 29, 2023
3d4ee4f
Replaced CRC lookup table with shift, XOR CRC_poly method
ronitnag04 Dec 14, 2023
1df3eda
Merge branch 'main' into d2dadapter-crc
ronitnag04 Feb 24, 2024
71d1365
Merge branch 'd2dadapter-crc' of https://github.com/ucb-ucie/uciedigi…
ronitnag04 Feb 24, 2024
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
267 changes: 267 additions & 0 deletions src/main/scala/d2dadapter/CRC16Lookup8Bit.scala
Original file line number Diff line number Diff line change
@@ -0,0 +1,267 @@
package edu.berkeley.cs.ucie.digital.d2dadapter

import chisel3._

class CRC16Lookup {
ethanwu10 marked this conversation as resolved.
Show resolved Hide resolved

// Lookup table for CRC-16 (0x8005) polynomial

ronitnag04 marked this conversation as resolved.
Show resolved Hide resolved
val table = VecInit(
0x0000.U,
0x8005.U,
0x800f.U,
0x000a.U,
0x801b.U,
0x001e.U,
0x0014.U,
0x8011.U,
0x8033.U,
0x0036.U,
0x003c.U,
0x8039.U,
0x0028.U,
0x802d.U,
0x8027.U,
0x0022.U,
0x8063.U,
0x0066.U,
0x006c.U,
0x8069.U,
0x0078.U,
0x807d.U,
0x8077.U,
0x0072.U,
0x0050.U,
0x8055.U,
0x805f.U,
0x005a.U,
0x804b.U,
0x004e.U,
0x0044.U,
0x8041.U,
0x80c3.U,
0x00c6.U,
0x00cc.U,
0x80c9.U,
0x00d8.U,
0x80dd.U,
0x80d7.U,
0x00d2.U,
0x00f0.U,
0x80f5.U,
0x80ff.U,
0x00fa.U,
0x80eb.U,
0x00ee.U,
0x00e4.U,
0x80e1.U,
0x00a0.U,
0x80a5.U,
0x80af.U,
0x00aa.U,
0x80bb.U,
0x00be.U,
0x00b4.U,
0x80b1.U,
0x8093.U,
0x0096.U,
0x009c.U,
0x8099.U,
0x0088.U,
0x808d.U,
0x8087.U,
0x0082.U,
0x8183.U,
0x0186.U,
0x018c.U,
0x8189.U,
0x0198.U,
0x819d.U,
0x8197.U,
0x0192.U,
0x01b0.U,
0x81b5.U,
0x81bf.U,
0x01ba.U,
0x81ab.U,
0x01ae.U,
0x01a4.U,
0x81a1.U,
0x01e0.U,
0x81e5.U,
0x81ef.U,
0x01ea.U,
0x81fb.U,
0x01fe.U,
0x01f4.U,
0x81f1.U,
0x81d3.U,
0x01d6.U,
0x01dc.U,
0x81d9.U,
0x01c8.U,
0x81cd.U,
0x81c7.U,
0x01c2.U,
0x0140.U,
0x8145.U,
0x814f.U,
0x014a.U,
0x815b.U,
0x015e.U,
0x0154.U,
0x8151.U,
0x8173.U,
0x0176.U,
0x017c.U,
0x8179.U,
0x0168.U,
0x816d.U,
0x8167.U,
0x0162.U,
0x8123.U,
0x0126.U,
0x012c.U,
0x8129.U,
0x0138.U,
0x813d.U,
0x8137.U,
0x0132.U,
0x0110.U,
0x8115.U,
0x811f.U,
0x011a.U,
0x810b.U,
0x010e.U,
0x0104.U,
0x8101.U,
0x8303.U,
0x0306.U,
0x030c.U,
0x8309.U,
0x0318.U,
0x831d.U,
0x8317.U,
0x0312.U,
0x0330.U,
0x8335.U,
0x833f.U,
0x033a.U,
0x832b.U,
0x032e.U,
0x0324.U,
0x8321.U,
0x0360.U,
0x8365.U,
0x836f.U,
0x036a.U,
0x837b.U,
0x037e.U,
0x0374.U,
0x8371.U,
0x8353.U,
0x0356.U,
0x035c.U,
0x8359.U,
0x0348.U,
0x834d.U,
0x8347.U,
0x0342.U,
0x03c0.U,
0x83c5.U,
0x83cf.U,
0x03ca.U,
0x83db.U,
0x03de.U,
0x03d4.U,
0x83d1.U,
0x83f3.U,
0x03f6.U,
0x03fc.U,
0x83f9.U,
0x03e8.U,
0x83ed.U,
0x83e7.U,
0x03e2.U,
0x83a3.U,
0x03a6.U,
0x03ac.U,
0x83a9.U,
0x03b8.U,
0x83bd.U,
0x83b7.U,
0x03b2.U,
0x0390.U,
0x8395.U,
0x839f.U,
0x039a.U,
0x838b.U,
0x038e.U,
0x0384.U,
0x8381.U,
0x0280.U,
0x8285.U,
0x828f.U,
0x028a.U,
0x829b.U,
0x029e.U,
0x0294.U,
0x8291.U,
0x82b3.U,
0x02b6.U,
0x02bc.U,
0x82b9.U,
0x02a8.U,
0x82ad.U,
0x82a7.U,
0x02a2.U,
0x82e3.U,
0x02e6.U,
0x02ec.U,
0x82e9.U,
0x02f8.U,
0x82fd.U,
0x82f7.U,
0x02f2.U,
0x02d0.U,
0x82d5.U,
0x82df.U,
0x02da.U,
0x82cb.U,
0x02ce.U,
0x02c4.U,
0x82c1.U,
0x8243.U,
0x0246.U,
0x024c.U,
0x8249.U,
0x0258.U,
0x825d.U,
0x8257.U,
0x0252.U,
0x0270.U,
0x8275.U,
0x827f.U,
0x027a.U,
0x826b.U,
0x026e.U,
0x0264.U,
0x8261.U,
0x0220.U,
0x8225.U,
0x822f.U,
0x022a.U,
0x823b.U,
0x023e.U,
0x0234.U,
0x8231.U,
0x8213.U,
0x0216.U,
0x021c.U,
0x8219.U,
0x0208.U,
0x820d.U,
0x8207.U,
0x0202.U,
)
}
88 changes: 88 additions & 0 deletions src/main/scala/d2dadapter/CRCGenerator.scala
Original file line number Diff line number Diff line change
@@ -0,0 +1,88 @@
package edu.berkeley.cs.ucie.digital.d2dadapter

import chisel3._
import chisel3.util._
import chisel3.util.Decoupled
ronitnag04 marked this conversation as resolved.
Show resolved Hide resolved
import edu.berkeley.cs.ucie.digital.d2dadapter.CRC16Lookup
ronitnag04 marked this conversation as resolved.
Show resolved Hide resolved

/** Generates the CRC of data using the polynomial x^16 + x^15 + x^2 + 1
*/

class CRCGenerator(width: Int) extends Module { // width is word size in bits (must be whole number of bytes)
ronitnag04 marked this conversation as resolved.
Show resolved Hide resolved
val io = IO(new Bundle {
val rst = Input(Bool())

val message = Flipped(Decoupled(Bits(width.W)))

val crc0_out = Output(UInt(8.W)) // CRC 0 Byte output
val crc1_out = Output(UInt(8.W)) // CRC 1 Byte output
val crc_val = Output(
Bool(),
) // Signal to consumer that data on crc0_out and crc1_out are valid
})

// Output data registers
val crc0 = RegInit(UInt(8.W), 0.U)
val crc1 = RegInit(UInt(8.W), 0.U)

// Output signal registers
val message_ready = RegInit(Bool(), false.B)
val crc_val = RegInit(Bool(), false.B)

// CRC calculating registers
val step = RegInit(
UInt(log2Ceil(width / 8 + 1).W),
0.U,
ronitnag04 marked this conversation as resolved.
Show resolved Hide resolved
) // Store number of bytes in width bits
val message_bits = RegInit(
Bits(width.W),
0.U,
) // Latches full word of data when message_ready and data_val

// CRC calculating table
val lookup = new CRC16Lookup

// Propogate output data register
io.crc0_out := crc0
io.crc1_out := crc1

// Signal Valid and Ready
io.crc_val := crc_val
io.message.ready := message_ready

// Reset logic
when(io.rst) {
ronitnag04 marked this conversation as resolved.
Show resolved Hide resolved
// Reset output data registers
crc0 := 0.U
crc1 := 0.U

// Signal Valid and Ready
crc_val := true.B
message_ready := true.B

// Reset CRC calculating registers
step := 0.U
}

// Latch data on message_ready and data_val
when(io.message.valid & io.message.ready) {
ronitnag04 marked this conversation as resolved.
Show resolved Hide resolved
step := (width / 8).U // Number of bytes in word
message_bits := io.message.bits
crc_val := false.B
message_ready := false.B
}

// Computation not finished when step is not 0
when(step > 0.U) {
crc1 := crc0 ^ lookup
.table(crc1 ^ message_bits(width - 1, width - 8))(15, 8)
crc0 := lookup.table(crc1 ^ message_bits(width - 1, width - 8))(7, 0)
message_bits := message_bits << 8
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Is this endianness correct? This implementation treats message as one big-endian integer and CRC's bytes from most-significant-byte to LSB (as documented); not sure if this is what we want though.

Copy link
Collaborator Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Yeah, it's a little unconventional compared to what I normally see for CRC calculations, but the results of this CRC generator match the results of the design the UCIe1.0 spec has in the appendix (where they just selectively xor the 1024 bits of the message for each of the 16 crc bits). I ran a simulation of the xor'ing method in python to generate the test cases I listed in the test module.

step := step - 1.U
crc_val := false.B
message_ready := false.B
}.otherwise {
crc_val := true.B
message_ready := true.B
}
}
Loading