Scrambler Module #57
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Scrambler Module #57
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rahulk29
reviewed
Nov 18, 2023
src/main/scala/Scrambler.scala
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| LFSR.io.seed.bits := VecInit(io.seed.asBools) | ||
| LFSR.io.seed.valid := (reset.asBool) | ||
| val LFSR_result = LFSR.io.out | ||
| // printf(cf"$LFSR_result.asUInt") |
rahulk29
reviewed
Nov 18, 2023
src/main/scala/Scrambler.scala
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| LFSR.io.increment := io.valid | ||
| LFSR.io.seed.bits := VecInit(io.seed.asBools) | ||
| LFSR.io.seed.valid := (reset.asBool) | ||
| val LFSR_result = LFSR.io.out |
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do you need this? does LFSR.io.out.asUInt not work?
rahulk29
reviewed
Nov 18, 2023
| c.clock.step() | ||
| c.io.valid.poke(true.B) | ||
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| c.io.data_in(0).poke(1.U(16.W)) |
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would be good to add a few more clock steps to the test
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Multi-lane scrambler module with simple test