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Enum for Rdi sb width #58

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7 changes: 4 additions & 3 deletions src/main/scala/interfaces/Rdi.scala
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@ package interfaces
import chisel3._
import chisel3.util._

case class RdiParams(width: Int, sbWidth: Int)
case class RdiParams(width: Int, sbWidth: RdiSbWidth.Value)

/** The raw D2D interface (RDI), from the perspective of the D2D Adapter. */
class Rdi(rdiParams: RdiParams) extends Bundle {
Expand Down Expand Up @@ -80,8 +80,9 @@ class Rdi(rdiParams: RdiParams) extends Bundle {
val lpWakeReq = Output(Bool())
val plWakeAck = Input(Bool())

val plConfig = Flipped(Valid(UInt(rdiParams.sbWidth.W)))
val sbWidth = rdiParams.sbWidth.id
val plConfig = Flipped(Valid(UInt(sbWidth.W)))
val plConfigCredit = Input(Bool())
val lpConfig = Valid(UInt(rdiParams.sbWidth.W))
val lpConfig = Valid(UInt(sbWidth.W))
val lpConfigCredit = Output(Bool())
}
6 changes: 6 additions & 0 deletions src/main/scala/interfaces/Types.scala
Original file line number Diff line number Diff line change
Expand Up @@ -96,3 +96,9 @@ object FlitFormat extends ChiselEnum {
val latencyOpt256NoOptional = Value(0x5.U(4.W))
val latencyOpt256Optional = Value(0x6.U(4.W))
}

object RdiSbWidth extends Enumeration {
val width8 = Value(8)
val width16 = Value(16)
val width32 = Value(32)
}